AI 中文总结
研究针对3D集成电路热问题，提出Chiplet3D布局规划器，支持芯片多种旋转翻转，从精确引脚位置测线长，用卷积嵌入混合整数线性规划准确跟踪热扩散，实验表明其能有效减少线长、降低峰值温度和热不均匀性，优化引脚与热场。
AI 中文摘要
随着传统摩尔定律的放缓，3D集成电路通过垂直堆叠多个有源芯片来维持性能提升。然而，垂直堆叠会使热量被困在内部，导致温度成为设计关注点。尽管可在不同设计阶段解决热问题，但布局规划是最早且最具成本效益的阶段。以往方法存在局限性，本文提出Chiplet3D，一种用于双芯片3D集成电路的引脚和热感知布局规划器。它支持所有四种旋转和两种翻转，从精确引脚位置测量线长，在热方面，用快速、粗略的卷积场取代先前基于功率的不准确度量，直接嵌入混合整数线性规划以准确跟踪真实3D热扩散。在ICCAD'24 ATPlace基准测试上评估，与SOTA基线相比，平均线长减少39% - 43%，峰值温度降低45.9$^\circ$C，热不均匀性降低56%。结果表明通过共同优化引脚对齐和热场，Chiplet3D在热感知布局和互连效率之间建立了更强的帕累托前沿。
英文摘要
As traditional Moore's Law scaling slows down, 3D-ICs stack multiple active dies vertically to sustain performance scaling. However, this vertical stacking traps heat inside, making temperature a design concern. Although we can fix thermal issues at different design steps, floorplanning is the earliest and most cost-effective stage to solve it. Previous methods handle this by assuming wires connect to block centers and estimating temperature through simplistic power-based calculations, but these assumptions mislead their wirelength optimization and leave hotspots unresolved. To address these limitations, we present Chiplet3D, a pin- and thermal-aware floorplanner for two-die 3D-ICs. To achieve pin-awareness, it supports all four rotations and two flips, measuring wirelength from exact pin locations so the solver can flip or rotate blocks to pull connected pins closer. On the thermal side, Chiplet3D replaces the inaccurate power-based metrics of prior work with a fast, coarse convolution field embedded directly in a mixed-integer linear program (MILP) to accurately track the true 3D heat spread. We evaluate Chiplet3D on the ICCAD'24 ATPlace benchmarks, validating every temperature with a golden 3D-ICE simulation. Chiplet3D reduces wirelength by 39\%--43\% on average (and up to 62\% in the best case), while lowering peak temperatures by up to 45.9$^\circ$C and reducing thermal non-uniformity by up to 56\% compared to the SOTA baselines. Overall, these results demonstrate that by co-optimizing pin alignment and thermal fields, Chiplet3D establishes a stronger Pareto frontier between thermal-aware layout and interconnect efficiency.
Comments8 pages, 6 figures
