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ECG-LDC:一种用于心电图心律失常分类的硬件高效低维计算框架

ECG-LDC: A Hardware-Efficient Low-Dimensional Computing Framework for ECG Arrhythmia Classification

Anh Tran, Khanh Tran, Cuong Do

arXiv 2607.09680首次发表:更新:

发表机构

University of Pennsylvania; VinUniversity; VinUni–Illinois Smart Health Center(宾夕法尼亚大学; 文大学; 文大学-伊利诺伊智能健康中心)

机构由 AI 辅助整理,请以论文原文为准。

AI 中文总结

针对可穿戴设备中心电图心律失常分类需求,提出软硬件协同设计框架ECG-LDC,采用双编码器架构及低维计算,经数据预处理、模型训练和硬件加速器架构原型实现,准确率高且内存占用低,适合资源受限可穿戴平台实时检测心律失常。

AI 中文摘要

可穿戴设备中的连续心脏监测需要同时具备准确性、高能效且可在资源受限硬件上部署的分类器。虽然深度神经网络方法在心电图心律失常检测中展现出高分类准确率,但因其大量参数和对乘法累加密集型操作的依赖,不适用于低成本边缘平台。本文提出ECG-LDC,一种软硬件协同设计框架,采用低维计算进行实时心电图心律失常分类。它采用双编码器架构及专用码本,能有效捕捉心搏内和心搏间心脏动态。该框架涵盖数据预处理、模型训练及基于Pynq-Z2平台的硬件加速器架构原型。采用二进制表示和基于异或/同或的操作,ECG-LDC准确率达97.18%,内存占用仅3.86 kB。与SOTA TinyML分类器相比,准确率牺牲约1.8%,但内存使用减少11至570倍;在基于FPGA的五类心律失常分类器中,它具有最高准确率,LUT减少2.4倍且零DSP块使用,适用于资源受限可穿戴平台的实时心律失常检测。

英文摘要

Continuous cardiac monitoring in wearable devices demands classifiers that are simultaneously accurate, energy-efficient, and deployable on resource-constrained hardware. While deep neural network approaches have demonstrated high classification accuracy for electrocardiogram (ECG) arrhythmia detection, their substantial parameter counts and reliance on multiply-accumulate-intensive operations make them impractical for low-cost edge platforms. In this work, we propose ECG-LDC, a hardware-software co-design framework that adapts Low-Dimensional Computing (LDC) for real-time ECG arrhythmia classification. ECG-LDC employs a dual-encoder architecture with dedicated value and feature codebooks to independently encode morphological waveform features and RR-interval temporal features, enabling effective capture of both intra-beat and inter-beat cardiac dynamics. The framework encompasses data preprocessing, model training, and a hardware accelerator architecture prototyped on the Pynq-Z2 platform. Implemented using binary representations and XOR/XNOR-based operations, ECG-LDC achieves $97.18\%$ accuracy with a memory footprint of only $3.86\ \text{kB}$. ECG-LDC sacrifices approximately $1.8\%$ accuracy versus SOTA TinyML classifiers but achieves $11$~$ 570\times$ reduction in memory usage; among FPGA-based five-class arrhythmia classifiers, it delivers the highest accuracy with up to $2.4\times$ fewer LUTs and zero DSP block utilization, affirming its suitability for real-time arrhythmia detection on resource-constrained wearable platforms.

Comments10 pages, 5 figures, 6 tables

论文原文

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