AI 中文总结
该研究针对开源CMOS生态系统中射频集成电路设计无源器件模型缺乏的问题，提出在130nm BiCMOS技术下实现2.4GHz小数分频PLL的设计，采用交叉耦合差分LC-VCO与定制电感，展示了全开源流程设计的可行性及良好性能。
AI 中文摘要
利用开源互补金属氧化物半导体（CMOS）生态系统进行射频（RF）集成电路设计，如用于锁相环（PLL）时，因缺乏可靠无源器件模型而受限，尤其片上螺旋电感。以往工作依赖基于环形振荡器的压控振荡器（VCO），相位噪声性能较差。本文展示了在IHP SG13G2 130nm BiCMOS开源技术中实现的2.4GHz II型小数分频PLL。所提设计采用交叉耦合差分LC-VCO与定制螺旋电感集成，该电感通过OpenEMS中的开源电磁建模工作流程开发。优化后的电感在2.45GHz时实现4nH电感和16.8的品质因数。LC-VCO灵敏度约为120MHz/V，PLL在1MHz频偏时相位噪声为-100.8dBc/Hz。完整PLL采用全开源电子设计自动化（EDA）流程实现，总面积为930um x 666um（约0.619mm2），功耗12.73mW，证明了在开源CMOS IC设计生态系统中进行RF集成电路设计的可行性。
英文摘要
Radio frequency (RF) integrated circuit design using the open-source complementary Metal-Oxide semiconductor (CMOS) ecosystem, such as for phase-locked loops (PLLs), is limited by the absence of reliable passive device models, particularly on-chip spiral inductors. Consequently, prior work relies on ring-oscillator-based voltage-controlled oscillators (VCOs) with degraded phase noise performance. This work presents a 2.4 GHz type-II fractional-N PLL implemented in the IHP SG13G2 130 nm BiCMOS open-source technology. The proposed design employs a cross-coupled differential LC-VCO integrated with a custom-designed spiral inductor, developed using an open-source electromagnetic modelling workflow in OpenEMS. The optimized inductor achieves 4 nH inductance with a quality factor of 16.8 at 2.45 GHz. The LC-VCO sensitivity is approximately 120 MHz/V, while the PLL phase noise is -100.8 dBc/Hz at 1 MHz offset. The complete PLL is realized using a fully open-source electronic design automation (EDA) flow, occupying a total area of 930 um x 666 um (~0.619 mm2) and consuming 12.73 mW, demonstrating the feasibility of RF integrated circuit design in an open-source CMOS IC design ecosystem.
Journal ref2026 22nd International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuits Design (SMACD)
DOI：10.1109/SMACD70206.2026.11647761
