用于ePIC dRICH探测器的基于脉冲神经网络的在线数据约简：时间符合编码器和分布式脉冲神经网络
Online Data Reduction with Spiking Neural Networks: A Temporal-Coincidence Encoder and Distributed SNN for the ePIC dRICH Detector
AI总结：
针对电子离子对撞机ePIC实验中dRICH探测器高数据率及暗计数率问题，提出基于脉冲神经网络的两阶段在线数据约简方法，包括时间符合编码器和分布式网络，在模拟事件中效果良好，硬件验证了单子扇区管道。
摘要：
电子离子对撞机（EIC）的ePIC实验中的双辐射器环形成像切伦科夫（dRICH）探测器将以100 MHz的束团交叉率读出约320,000个硅光电倍增管（SiPM）通道。在实验寿命期间，SiPM的暗计数率（DCR）预计将上升至每个通道300 kHz，使输出带宽饱和，需要至少五倍的在线数据约简因子。大多数交叉仅包含不相关的DCR命中，而真正的切伦科夫命中聚集在10 ns交叉窗口的约2 ns内：这是一个内在的时间辨别问题。我们提出了一种基于脉冲神经网络（SNN）的两阶段在线数据约简管道。第一阶段是每个光电探测单元的泄漏积分发放（LIF）时间符合编码器，它将原始SiPM命中转换为稀疏脉冲流，在应用任何学习分类器之前实现超过90%的数据稀疏化。第二阶段是部署在FELIX-155 DAM板和专用触发处理器板上的分布式SNN（30个子扇区网络加上一个聚合网络），将每个交叉分类为仅噪声或信号+噪声。在模拟的ePIC事件上，该系统在整个DCR范围内以至少80%的真阴性率达到94%以上的真阳性率；一种可选的早期退出策略将平均分类延迟降低到约2个算法时间步长，代价是在两个指标上降低几个百分点。在AMD Versal Premium FPGA上的硬件概念验证，将LIF编码器与AIGOR多核神经形态架构集成，以约1.7 MHz的吞吐量验证了单个子扇区管道；正在进行的工作通过确定的推理结构优化目标是100 MHz。该方法可能与其他高速定时驱动的探测器应用相关。
英文摘要：
The dual-radiator Ring Imaging Cherenkov (dRICH) detector of the ePIC experiment at the Electron-Ion Collider (EIC) will read out $\sim$320,000 silicon photomultiplier (SiPM) channels at a bunch-crossing rate of 100 MHz. The dark count rate (DCR) of the SiPMs is expected to rise up to 300 kHz per channel over the experiment lifetime, saturating the output bandwidth and requiring an online data reduction factor of at least five. Most crossings contain only uncorrelated DCR hits, while genuine Cherenkov hits cluster within $\sim$2 ns of the 10 ns crossing window: an intrinsically temporal discrimination problem. We present a two-stage online data reduction pipeline based on spiking neural networks (SNNs). The first stage is a per-photodetection-unit leaky-integrate-and-fire (LIF) temporal coincidence encoder that converts raw SiPM hits into a sparse spike stream, achieving over 90% data sparsification before any learned classifier is applied. The second stage is a distributed SNN (30 sub-sector networks plus an aggregation network) deployed on FELIX-155 DAM boards and a dedicated Trigger Processor board, classifying each crossing as Noise-Only or Signal+Noise. On simulated ePIC events the system reaches a true positive rate above 94% at a true negative rate of at least 80% across the full DCR range; an optional early-exit strategy reduces the average classification latency to $\sim$2 algorithmic timesteps at the cost of a few percentage points on both metrics. A hardware proof-of-concept on an AMD Versal Premium FPGA, integrating the LIF encoder with the AIGOR multi-core neuromorphic architecture, validates a single sub-sector pipeline at $\sim$1.7 MHz throughput; ongoing work targets 100 MHz through an identified set of optimizations of the inference fabric. The methodology may be relevant to other timing-driven detector applications at high rate.
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