AsyncLane: 扩散语言模型解码中精炼与推进的解耦
AsyncLane: Decoupling Refinement from Advancement in Diffusion Language Model Decoding
AI总结：
提出AsyncLane，一种无需训练的解码调度器，通过将生成过程分叉为精炼和推进两个通道，解耦块间依赖，在保持质量的同时显著提升扩散语言模型的解码吞吐量。
摘要：
块级半自回归解码是扩散大语言模型（DLMs）的标准推理范式，但它强制块之间存在严格依赖：当前块完全解码或去噪预算耗尽之前，下一个块无法开始。我们观察到，一旦一个块暴露出可靠的分隔符边界或稳定的语义前缀，续写生成无需等待每个残差标记被解析。我们提出AsyncLane，一种无需训练的解码调度器，将精炼与推进解耦。AsyncLane在观察到的分隔符边界处将生成通道分叉为精炼通道和续写生成通道：前缀保持可编辑，而续写在前缀精炼完成之前推进。由此产生的通道树记录解码依赖关系和输出顺序，而执行则在活跃通道集上进行。为了使这种异步调度在双向注意力下高效，AsyncLane结合了共享前缀通道批处理、前瞻草稿重用、级联终止以及带有刷新-逻辑重用的紧凑缓存刷新，防止模型调用成本随通道数量线性增长。AsyncLane是块级DLM采样器的即插即用替代品，无需重新训练。在数学推理和代码生成实验表明，AsyncLane在保持竞争性质量的同时持续提高吞吐量。在LLaDA和Dream骨干网络上，AsyncLane在所有评估的基准长度设置中实现了最高的TPS；相对于最快的竞争基线，它在LLaDA上达到2.95倍峰值加速，在Dream上达到3.04倍，在较长生成预算下增益尤为显著。
英文摘要：
Block-wise semi-autoregressive decoding is the standard inference paradigm for diffusion large language models (DLMs), but it imposes a strict dependency between blocks: the next block cannot begin until the current block is fully decoded or its denoising budget is exhausted. We observe that once a block exposes a reliable delimiter boundary or stable semantic prefix, continuation generation need not wait for every residual token to be resolved. We propose AsyncLane, a training-free decoding scheduler that decouples refinement from advancement. AsyncLane forks a generate lane at observed delimiter boundaries into a refine lane and a continuation generate lane: the prefix remains editable, while the continuation advances before prefix refinement finishes. The resulting lane tree records decoding dependencies and output order, while execution proceeds over the active lane set. To make this asynchronous schedule efficient under bidirectional attention, AsyncLane combines shared-prefix lane batching, lookahead draft reuse, cascading termination, and compact cache refresh with refresh-logit reuse, preventing model-call cost from scaling directly with the number of lanes. AsyncLane is a drop-in replacement for block-wise DLM samplers and requires no retraining. Experiments on mathematical reasoning and code generation show that AsyncLane consistently improves throughput while maintaining competitive quality. Across LLaDA and Dream backbones, AsyncLane achieves the highest TPS in all evaluated benchmark-length settings; relative to the fastest competing baseline, it reaches peak speedups of 2.95x on LLaDA and 3.04x on Dream, with especially large gains under longer generation budgets.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
