探索基于LLM的Verilog代码生成：数据高效微调与测试平台自动化
Exploring LLM-based Verilog Code Generation with Data-Efficient Fine-Tuning and Testbench Automation
AI总结：
本文提出利用多智能体模型生成高质量微调数据的测试平台，实现比现有方法更少训练数据下的Verilog生成性能。
摘要：
近年来，大语言模型在代码生成方面取得进展，但在硬件描述语言中的应用仍有限。此外，这些模型的训练数据和测试平台通常稀缺。本文提出一个工作流程，利用多智能体模型生成高质量微调数据的测试平台。通过自动化测试平台创建，微调后的模型在Refined VerilogEval v2基准上的性能与最先进方法相当，但使用更少的训练数据。本研究为未来基于LLM的HDL生成和自动化验证工作奠定了基础。
英文摘要：
Recent advances in large language models have improved code generation, but their use in hardware description languages is still limited. Moreover, training data and testbenches for these models are often scarce. This paper presents a workflow that uses multi-agent models to generate testbenches for high-quality fine-tuning data. By automating testbench creation, the fine-tuned model for the specification-to-Verilog task achieves performance comparable to state-of-the-art methods on the refined VerilogEval v2 benchmark while using less training data. This study provides a basis for future work on LLM-based HDL generation and automated verification.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
