PG-MDP:基于轮廓的内存依赖性预测用于面积受限的核心
PG-MDP: Profile-Guided Memory Dependence Prediction for Area-Constrained Cores
AI总结:
本文提出PG-MDP,通过 opcode 标记一致的内存独立负载并移除 MDP 工作集,减少 MDP 查询率和假依赖,提升 IPC 性能。
摘要:
内存依赖性预测(MDP)是一种推测技术,用于确定给定负载将依赖哪些存储。在各种应用中,如节能或边缘系统,面积受限的核心越来越相关,且通常有有限的 MDP 表空间。这导致假依赖率高,因为内存独立负载与无关的预测器条目冲突,导致处理器流水线停顿。传统方法通过增加预测器大小或复杂度来解决,但这种方法在面积受限的核心上并不理想。本文提出针对预测器工作集的方法与扩大预测器同样有效,并能提供与大预测器竞争的性能,同时仍使用非常小的预测器。本文引入了基于轮廓的内存依赖性预测(PG-MDP),一种软件协同设计,通过 opcode 标记一致的内存独立负载并将其移出 MDP 工作集。这些负载在调度时绕过查询 MDP,总是尽早发出。在 SPEC2017 CPU intspeed 上,PG-MDP 将 MDP 查询率减少了 79%,假依赖减少了 77%,并通过小型模拟核心提升了 1.47% 的几何平均 IPC(接近使用 16 倍预测器条目时的性能),且无面积成本和额外指令带宽。
英文摘要:
Memory Dependence Prediction (MDP) is a speculative technique to predict which stores, if any, a given load will depend on. Area-constrained cores are increasingly relevant in various applications such as energy-efficient or edge systems, and often have limited space for MDP tables. This leads to a high rate of false dependencies as memory independent loads alias with unrelated predictor entries, causing unnecessary stalls in the processor pipeline. The conventional way to address this problem is with greater predictor size or complexity, but this is unattractive on area-constrained cores. This paper demonstrates that targeting the predictor working set delivers the majority of available performance without scaling any hardware structures. We achieve this with profile-guided memory dependence prediction (PG-MDP), a hardware-software co-design to label consistently memory independent loads via their opcode and remove them from the MDP working set. These loads bypass querying the MDP and always issue as soon as possible. In the event that a labeled load incorrectly passes a store to the same address, a rollback is triggered as usual but no new MDP entry is created. Across the SPECspeed 2017 suites, PG-MDP reduces MDP load queries by 80%, false dependencies by 84%, and improves geomean IPC for a small (ROB=128) simulated core by 4.6% (to within 1.2% of the IPC when using 8x more predictor entries), with no area cost and no additional instruction bandwidth.
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