多GPU扩展机箱中反向地址转换开销分析
Analyzing Reverse Address Translation Overheads in Multi-GPU Scale-Up Pods
AI总结：
本文研究多GPU扩展机箱中反向地址转换对All-to-All集体通信性能的影响，提出优化方法以减少延迟，提升推理工作负载的吞吐量和可扩展性。
摘要：
分布式机器学习工作负载严重依赖多GPU、多节点系统中的集体通信。新兴的扩展织物，如NVLink和UALink，使节点间可以直接内存访问，但引入了关键的目的地侧转换步骤：将网络物理地址（NPAs）转换为系统物理地址（SPAs），我们称之为反向转换（反向地址转换）。尽管其重要性，反向转换的性能影响仍不明确。本文首次系统研究大规模GPU集群中的反向转换。使用扩展的ASTRA-sim框架与Omnet++作为网络后端，我们建模链路MMU和链路TLB，并评估其在不同输入大小和GPU数量下的All-to-All集体通信效果。分析显示，冷TLB缺失主导小型、低延迟集体通信的延迟，导致性能下降高达1.4倍，而较大集体通信受益于预热缓存，且超大TLB带来递减收益。基于这些观察，我们提出两种优化途径：融合预转换内核以重叠反向转换与计算，以及软件引导的TLB预取以主动填充可能需要的条目。这些技术旨在隐藏转换延迟，特别是对于小型集体通信，提高推理工作负载的吞吐量和可扩展性。本研究为设计高效的目的地侧转换机制奠定了基础。
英文摘要：
Distributed ML workloads rely heavily on collective communication across multi-GPU, multi-node systems. Emerging scale-up fabrics, such as NVLink and UALink, enable direct memory access across nodes but introduce a critical destination-side translation step: translating Network Physical Addresses (NPAs) to System Physical Addresses (SPAs), which we term Reverse Translation (Reverse Address Translation). Despite its importance, the performance impact of Reverse Address Translation remains poorly understood. In this work, we present the first systematic study of Reverse Address Translation in large-scale GPU clusters. Using an extended ASTRA-sim framework with Omnet++ as the network backend, we model Link MMUs and Link TLBs and evaluate their effect on All-to-All collective communication across varying input sizes and GPU counts. Our analysis shows that cold TLB misses dominate latency for small, latency-sensitive collectives, causing up to 1.4x performance degradation, while larger collectives benefit from warmed caches and experience diminishing returns from over sized TLBs. Based on these observations, we propose two avenues for optimization: fused pre-translation kernels that overlap Reverse Address Translation with computation and software-guided TLB prefetching to proactively populate likely-needed entries. These techniques aim to hide translation latency, particularly for small collectives, improving throughput and scalability for inference workloads. Our study establishes a foundation for designing efficient destination-side translation mechanisms in large-scale multi-GPU systems.
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