ARCS：具有拓扑感知图注意力和规格条件的自回归电路合成
ARCS: Autoregressive Circuit Synthesis with Topology-Aware Graph Attention and Spec Conditioning
AI总结：
ARCS通过结合图变分自编码器和流匹配模型，实现快速生成高精度模拟电路，其在拓扑和组件值上达到99.9%的模拟有效性，效率比传统方法提升40倍。
摘要：
本文提出ARCS（自回归电路合成），一种用于近似模拟电路生成的系统。ARCS能在毫秒内生成完整、可被SPICE模拟的电路设计（拓扑和元件值），而传统基于搜索的方法需要分钟级时间。混合流程结合了两个学习生成器，即图变分自编码器和流匹配模型，与基于SPICE的排名。在32种拓扑结构上，仅使用8次SPICE评估就实现了99.9%的模拟有效性（奖励6.43/8.0），比遗传算法少40倍。对于单模型推断，拓扑感知的图Transformer结合Best-of-3候选选择，在97ms内达到85%的模拟有效性，比随机搜索快600倍。关键技术贡献是将分组相对策略优化（GRPO）应用于多拓扑电路强化学习。GRPO通过每种拓扑的优势归一化解决REINFORCE的关键失败模式，即跨拓扑奖励分布不匹配，仅在500次RL步骤（10倍更少）内将模拟有效性提高9.6个百分点。语法约束解码还通过拓扑感知的标记遮蔽保证100%的结构有效性。
英文摘要：
This paper presents ARCS (Autoregressive Circuit Synthesis), a system for amortized analog circuit generation. ARCS produces complete, SPICE-simulatable designs (topology and component values) in milliseconds rather than the minutes required by search-based methods. A hybrid pipeline combines two learned generators, a graph VAE and a flow-matching model, with SPICE-based ranking. It achieves 99.9% simulation validity (reward 6.43/8.0) across 32 topologies using only 8 SPICE evaluations, 40x fewer than genetic algorithms. For single-model inference, a topology-aware Graph Transformer with Best-of-3 candidate selection reaches 85% simulation validity in 97ms, over 600x faster than random search. The key technical contribution adapts Group Relative Policy Optimization (GRPO) to multi-topology circuit reinforcement learning. GRPO resolves a critical failure mode of REINFORCE, cross-topology reward distribution mismatch, through per-topology advantage normalization. This improves simulation validity by +9.6 percentage points over REINFORCE in only 500 RL steps (10x fewer). Grammar-constrained decoding additionally guarantees 100% structural validity by construction via topology-aware token masking.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
