TinyIceNet：低功耗SAR海冰分割用于机载FPGA推断
TinyIceNet: Low-Power SAR Sea Ice Segmentation for On-Board FPGA Inference
AI总结：
TinyIceNet是一种专为机载FPGA设计的低功耗SAR海冰分割网络，通过架构简化和低精度量化实现高效准确的海冰制图。
摘要：
准确的海冰制图对于极地地区安全航海至关重要，其中快速变化的冰况需要及时可靠的信息。虽然Sentinel-1合成孔径雷达（SAR）提供了高分辨率、全天候的海冰观测，但传统的地面处理受限于下行带宽、延迟以及传输大量原始数据的能耗。机载处理，通过在卫星有效载荷中集成专用推理芯片，提供了一种变革性的替代方案，可以在轨道上生成可操作的海冰产品。在此背景下，我们提出了TinyIceNet，一种紧凑的语义分割网络，专为机载阶段开发（SOD）制图从双极化Sentinel-1 SAR影像设计，在严格的硬件和能耗限制下。TinyIceNet在AI4Arctic数据集上训练，结合SAR-aware的架构简化和低精度量化，以平衡精度和效率。该模型使用高级综合进行合成，并部署在Xilinx Zynq UltraScale+ FPGA平台上，展示了近实时推断，显著降低了能耗。实验结果表明，TinyIceNet在SOD分割上实现了75.216%的F1分数，同时将能耗降低2倍，凸显了芯片级硬件-算法协同设计在未来的空间 borne 和边缘AI系统中的潜力。
英文摘要：
Accurate sea ice mapping is essential for safe maritime navigation in polar regions, where rapidly changing ice conditions require timely and reliable information. While Sentinel-1 Synthetic Aperture Radar (SAR) provides high-resolution, all-weather observations of sea ice, conventional ground-based processing is limited by downlink bandwidth, latency, and energy costs associated with transmitting large volumes of raw data. On-board processing, enabled by dedicated inference chips integrated directly within the satellite payload, offers a transformative alternative by generating actionable sea ice products in orbit. In this context, we present TinyIceNet, a compact semantic segmentation network co-designed for on-board Stage of Development (SOD) mapping from dual-polarized Sentinel-1 SAR imagery under strict hardware and power constraints. Trained on the AI4Arctic dataset, TinyIceNet combines SAR-aware architectural simplifications with low-precision quantization to balance accuracy and efficiency. The model is synthesized using High-Level Synthesis and deployed on a Xilinx Zynq UltraScale+ FPGA platform, demonstrating near-real-time inference with significantly reduced energy consumption. Experimental results show that TinyIceNet achieves 75.216% F1 score on SOD segmentation while reducing energy consumption by 2x compared to full-precision GPU baselines, underscoring the potential of chip-level hardware-algorithm co-design for future spaceborne and edge AI systems.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
