FPGA上稀疏机器学习的实时数据压缩
Real-Time Stream Compaction for Sparse Machine Learning on FPGAs
AI总结：
本研究提出了一种FPGA上的实时数据压缩方法，通过优化稀疏性处理，实现高效的GNN硬件加速，适用于高吞吐量和低延迟的科学实验场景。
摘要：
机器学习算法在碰撞实验中的第一级触发器中被更频繁地使用，图神经网络（GNN）推动了基于FPGA的触发器的硬件需求超过了当前的最先进水平。为了满足高吞吐量和低延迟环境的严格要求，我们提出了一种延迟优化的预处理概念，通过移除动态输入稀疏性来实现高效的GNN硬件加速。我们的方法将来自大量先进先出接口的数据重新排列到连接到机器学习硬件加速器的较少FIFO接口上。为了在高吞吐量的同时最小化硬件利用率，我们开发了一种针对FPGA优化的分层稀疏压缩管道。我们用Chisel设计语言实现了这一概念作为开源硬件生成器。作为演示，我们实现了一个配置作为GNN基的第一级触发器中的预处理阶段，用于 Belle II探测器中的电磁量能器。此外我们评估了延迟、吞吐量、资源利用率和可扩展性，以适用于其他大规模科学实验。
英文摘要：
Machine learning algorithms are being used more frequently in the first-level triggers in collider experiments, with Graph Neural Networks pushing the hardware requirements of FPGA-based triggers beyond the current state of the art. To meet the stringent demands of high-throughput and low-latency environments, we propose a concept for latency-optimized preprocessing of sparse sensor data, enabling efficient GNN hardware acceleration by removing dynamic input sparsity. Our approach rearranges data coming from a large number of First-In-First-Out interfaces, typically sensor frontends, to a smaller number of FIFO interfaces connected to a machine learning hardware accelerator. In order to achieve high throughput while minimizing the hardware utilization, we developed a hierarchical sparsity compression pipeline optimized for FPGAs. We implemented our concept in the Chisel design language as an open-source hardware generator. For demonstration, we implemented one configuration of our module as preprocessing stage in a GNN-based first-level trigger for the Electromagnetic Calorimeter inside the Belle II detector. Additionally we evaluate latency, throughput, resource utilization, and scalability for a wide range of parameters, to enable broader use for other large scale scientific experiments.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
