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arXiv 2602.08415eess.SP

可重构低复杂度架构用于集成感知与通信系统中的高分辨率多普勒速度估计

Reconfigurable Low-Complexity Architecture for High Resolution Doppler Velocity Estimation in Integrated Sensing and Communication System

Aakanksha Tewari, Samarth Sharma Bhardwaj, Sumit J Darak, Shobha Sundar Ram

AI总结:

本文提出了一种可重构低复杂度架构,用于实现集成感知与通信系统中高分辨率多普勒速度估计,通过硬件软件协同设计实现算法级重构,提升执行效率并降低资源消耗。

摘要:

在毫米波集成感知与通信(ISAC)系统中,雷达和通信在时分方式下共享频谱和硬件。雷达快速检测并定位移动用户(MUs),之后通信通过雷达识别的窄波束进行。实现细粒度多普勒分辨率以区分MU杂波需要长相干处理间隔,这会减少通信时间和吞吐量。为了解决这个问题,我们提出了一种基于系统级芯片的可重构架构,用于多普勒估计的硬件软件协同设计。该架构支持算法级重构,动态切换于低复杂度、高速FFT基的粗略估计和高复杂度ESPRIT基的精细估计之间。我们引入了对ESPRIT的修改,实现了6.7倍的执行速度,同时将内存和乘法器的使用分别减少了79%和63%,而不会影响准确性。此外,该可重构架构在高SNR条件下可以切换到较低的慢时间包,进一步将延迟提高2倍,而性能无损失。

英文摘要:

In millimeter wave integrated sensing and communication (ISAC) systems for intelligent transportation, radar and communication share spectrum and hardware in a time division manner. Radar rapidly detects and localizes mobile users (MUs), after which communication proceeds through narrow beams identified by radar. Achieving fine Doppler resolution for MU clutter discrimination requires long coherent processing intervals, reducing communication time and throughput. To address this, we propose a reconfigurable architecture for Doppler estimation realized on a system on chip using hardware software codesign. The architecture supports algorithm level reconfiguration, dynamically switching between low-complexity, high-speed FFT-based coarse estimation and high complexity ESPRIT based fine estimation. We introduce modifications to ESPRIT that achieve 6.7 times faster execution while reducing memory and multiplier usage by 79% and 63%, respectively, compared to state of the art approaches, without compromising accuracy. Additionally, the reconfigurable architecture can switch to lower slow time packets under high SNR conditions, improving latency further by 2 times with no loss in performance.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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