编译量子正则语言状态
Compiling Quantum Regular Language States
AI总结：
本文提出了一种编译器，用于高效生成正则语言状态及其补集的量子态，通过结构化规范和中间表示实现资源优化。
摘要：
量子计算机的状态准备编译器通常处于两个极端：通用型的常规程序，将目标视为一个不透明的振幅向量，以及为少数知名状态家族定制的构造。我们询问是否可以设计一个编译器，接受简单的、具有结构的规范，同时提供可预测的资源保证。我们通过设计和实现一个用于正则语言状态（RLS）的量子状态准备编译器来回答这个问题：均匀的比特字符串超位置，以及它们的补集。用户通过（i）有限的比特字符串集，（ii）正则表达式，或（iii）确定性有限自动机（DFA），可选地带有补集标志来描述目标状态。通过将输入转换为DFA，对其进行最小化，并将其映射到最优的矩阵积状态（MPS），编译器获得一个中间表示（IR），该表示暴露并压缩了隐藏的结构。高效的DFA表示和最小化将昂贵的线性代数计算卸载，以换取更简单的自动机操作。正则语言前端与该IR的结合不仅为RLS提供了简洁的规范，还为可能需要指数级大状态描述的补集提供了简洁的规范。这使得RLS或其补集的状态准备在渐近资源和编译时间上相同。我们概述了两种面向硬件的后端：SeqRLSP，通过顺序生成产生线性深度、无辅助粒子的电路，适用于线性最近邻架构；TreeRLSP，通过树张量网络在全连接架构上实现对数深度。我们证明了深度和门数随系统大小和状态的最大Schmidt秩而变化的界限，并给出了显式的编译时间界限，以暴露我们方法的优势。我们实现了并评估了该流程。
英文摘要：
State preparation compilers for quantum computers typically sit at two extremes: general-purpose routines that treat the target as an opaque amplitude vector, and bespoke constructions for a handful of well-known state families. We ask whether a compiler can instead accept simple, structure-aware specifications while providing predictable resource guarantees. We answer this by designing and implementing a quantum state-preparation compiler for regular language states (RLS): uniform superpositions over bitstrings accepted by a regular description, and their complements. Users describe the target state via (i) a finite set of bitstrings, (ii) a regular expression, or (iii) a deterministic finite automaton (DFA), optionally with a complement flag. By translating the input to a DFA, minimizing it, and mapping it to an optimal matrix product state (MPS), the compiler obtains an intermediate representation (IR) that exposes and compresses hidden structure. The efficient DFA representation and minimization offloads expensive linear algebra computation in exchange of simpler automata manipulations. The combination of the regular-language frontend and this IR gives concise specifications not only for RLS but also for their complements that might otherwise require exponentially large state descriptions. This enables state preparation of an RLS or its complement with the same asymptotic resources and compile time. We outline two hardware-aware backends: SeqRLSP, which yields linear-depth, ancilla-free circuits for linear nearest-neighbor architectures via sequential generation, and TreeRLSP, which achieves logarithmic depth on all-to-all connectivity via a tree tensor network. We prove depth and gate-count bounds scaling with the system size and the state's maximal Schmidt rank, and we give explicit compile-time bounds that expose the benefit of our approach. We implement and evaluate the pipeline.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
