PCBSchemaGen: 奖励引导的LLM代码合成用于印刷电路板(PCB)原理图设计及结构化验证
PCBSchemaGen: Reward-Guided LLM Code Synthesis for Printed Circuit Boards (PCB) Schematic Design with Structured Verification
AI总结：
提出PCBSchemaGen框架，通过结构化验证器引导冻结的LLM生成可修复的PCB原理图，在无单元测试的领域实现高准确率。
摘要：
大多数LLM代码合成基准依赖于单元测试作为奖励预言，但PCB原理图设计没有这样的测试：正确性由真实IC封装和引脚级分配的结构化物理约束定义，每个任务的金标准参考不可用，且SPICE仿真无法验证原理图级正确性。我们提出PCBSchemaGen，一个无需训练的推理时框架，将冻结的LLM转变为可验证、可修复的PCB原理图生成器。该框架从IC数据手册中提取领域模式以约束LLM解码，将其与一个具有引脚级错误定位的确定性5层连续奖励验证器配对，并通过汤普森采样臂获取赌博机优化候选方案。我们在两个PCB基准上评估，涵盖22个统一电路领域的227个真实IC任务，包括一个从公开原理图导出的套件，作为完全保留的泛化测试（验证器、知识图谱库和提示在评估前冻结）。在我们的框架下，一个开放权重的31B模型（Gemma-4-31B）平均通过PCBBench任务的81.3%，且同一框架在两个基准间迁移时无需更改验证器代码；而基于相同Gemma-4-31B骨干网络的Circuitron式推理时提示基线在困难的系统级设计上崩溃。这表明在确定性结构验证器下的推理时优化是在没有单元测试预言的领域中实现无参考LLM代码合成的一般方法。我们的基准和确定性验证器在此https URL公开可用。
英文摘要：
Most LLM code-synthesis benchmarks rely on unit tests as the reward oracle, but PCB schematic design has none: correctness is defined by structured physical constraints over real IC packages and pin-level assignments, per-task golden references are unavailable, and SPICE simulation does not validate schematic-level correctness. We introduce PCBSchemaGen, a training-free inference-time framework that turns a frozen LLM into a verifiable, repairable PCB schematic generator. The framework induces a domain schema from IC datasheets to ground LLM decoding, pairs it with a deterministic 5-layer continuous-reward verifier with pin-level error localization, and refines candidates through a Thompson Sampling arm-acquiring bandit. We evaluate on 2 PCB benchmarks covering 227 real-IC tasks across 22 unified circuit domains, including a public-schematic-derived suite that serves as a fully held-out generalization test (verifier, KG library, and prompts frozen before any evaluation). Under our framework, an open-weight 31B model (Gemma-4-31B) passes 81.3% of PCBBench tasks on average, and the same framework transfers across both benchmarks with zero verifier code changes; a Circuitron-style inference-time prompting baseline on the same Gemma-4-31B backbone collapses on hard system-level designs. This suggests inference-time refinement under a deterministic structural verifier is a general recipe for reference-free LLM code synthesis in domains without unit-test oracles. Our benchmarks and deterministic verifier are publicly available at https://github.com/HZou9/PCBSchemaGen_v2.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
