单晶体管非易失性存储器的原位加密无需密度损失
In-Situ Encryption of Single-Transistor Nonvolatile Memories without Density Loss
AI总结：
本文提出了一种基于FeFET的单晶体管加密方案，实现加密存储器阵列与未加密阵列相同的存储密度，同时在吞吐量和延迟方面优于现有加密技术。
摘要：
非易失性存储器（NVMs）具有极低的漏电流功耗、高集成密度和数据保持性，但其非易失性也带来了数据暴露的风险。传统加密技术如高级加密标准（AES）会产生较大的面积开销和性能惩罚，因此推动了轻量级基于异或的原位加密方案，具有较低的面积和功耗要求。本文提出了一种超密集的单晶体管加密单元，利用铁电FET（FeFET）器件，据我们所知，这是首个消除异或方案中每加密单元需两个存储器器件要求的方案，使加密存储器阵列能够保持与未加密阵列相同的存储器件数量。关键思想是内存中的单FeFET异或方案，其中密文编码在器件阈值电压中，并利用FeFET的方向依赖性电流流动实现单周期解密；消除互补位存储也消除了需要两个写入周期的需要，从而实现更快的加密。我们扩展了该方法到多级单元（MLC）FeFETs，以每个晶体管存储多个比特。我们通过仿真和实验评估验证了所提出的想法。对128x128位阵列的分析显示，加密/解密吞吐量比先前FeFET工作高2倍，比AES提高了45.2倍/14.12倍，而使用神经网络基准的应用级评估显示，与先前FeFET和AES方案相比，平均延迟分别减少了50%和95%。
英文摘要：
Non-volatile memories (NVMs) offer negligible leakage power consumption, high integration density, and data retention, but their non-volatility also raises the risk of data exposure. Conventional encryption techniques such as the Advanced Encryption Standard (AES) incur large area overheads and performance penalties, motivating lightweight XOR-based in-situ encryption schemes with low area and power requirements. This work proposes an ultra-dense single-transistor encrypted cell using ferroelectric FET (FeFET) devices, which, to our knowledge, is the first to eliminate the two-memory-devices-per-encrypted-cell requirement in XOR-based schemes, enabling encrypted memory arrays to maintain the same number of storage devices as unencrypted arrays. The key idea is an in-memory single-FeFET XOR scheme, where the ciphertext is encoded in the device threshold voltage and leverages the direction-dependent current flow of the FeFET for single-cycle decryption; eliminating complementary bit storage also removes the need for two write cycles, allowing faster encryption. We extend the approach to multi-level-cell (MLC) FeFETs to store multiple bits per transistor. We validate the proposed idea through both simulation and experimental evaluations. Our analysis on a 128x128-bit array shows 2x higher encryption/decryption throughput than prior FeFET work and 45.2x/14.12x improvement over AES, while application-level evaluations using neural-network benchmarks demonstrate average latency reductions of 50% and 95% compared to prior FeFET-based and AES-based schemes, respectively.
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