采用双级放大器与有源纹波抵消以实现高 PSRR 和快速瞬态响应的宽输入 0.25 μm BCD LDO
A Wide-Input 0.25 um BCD LDO with Dual-Stage Amplifier and Active Ripple Cancellation for High PSRR and Fast Transient Response
AI总结：
本文设计 0.25 μm BCD 宽输入 LDO，通过双级误差放大器、有源纹波抵消和自适应快速反馈实现高 PSRR 与快速瞬态响应。
摘要：
随着片上系统（SoC）集成度不断提高，对同时具备高电源抑制比（PSRR）和快速瞬态响应的片上低压差线性稳压器（LDO）的需求持续增长。然而，传统 LDO 架构难以在宽输入电压范围内同时实现这些性能指标。本文提出一种采用 0.25 μm BCD 工艺实现的宽输入线性稳压器，可在保持低静态电流的同时获得高 PSRR 和迅速的负载瞬态性能。所提出的 LDO 采用双级误差放大器架构，并沿功率路径和误差放大器电源同时进行有源纹波抵消，以显著提升全频段 PSRR。文中引入自适应快速反馈支路以及片上频率补偿网络，在不损害稳定性的情况下加快瞬态响应。为指导设计，建立了两级 PSRR 分析模型和三频段 PSRR 解释框架。对 14 V 输出 LDO 的 Cadence Spectre 仿真表明，其低频 PSRR 达 -75 dB；在 50 μA 至 4 mA 负载阶跃期间，输出电压跌落保持在 0.65 V 以下，并在 16 μs 内恢复。这些结果验证了所提架构与分析的有效性，表明该设计满足模拟/RF SoC 和便携式电子设备的严格要求。
英文摘要：
Demand for on-chip low-dropout regulators (LDOs) with both high power-supply rejection ratio (PSRR) and fast transient response is growing as system-on-chip (SoC) integration increases. However, conventional LDO architectures face difficulty achieving these performance metrics simultaneously over wide input voltage ranges. This paper presents a wide-input linear regulator implemented in 0.25 um BCD technology that attains high PSRR and swift load-transient performance while maintaining low quiescent current. The proposed LDO employs a dual-stage error amplifier architecture and active ripple cancellation along both the power path and the error amplifier's supply to significantly enhance PSRR across frequency. An adaptive fast feedback branch together with an on-chip frequency compensation network is introduced to accelerate transient response without compromising stability. A two-stage PSRR analytical model and a three-frequency-band PSRR interpretation framework are developed to guide the design. Cadence Spectre simulations of the 14 V-output LDO demonstrate a -75 dB low-frequency PSRR, and during a 50 uA - 4 mA load step the output voltage droop is kept under 0.65 V with recovery within 16 us. These results validate the effectiveness of the proposed architecture and analysis, indicating that the design meets the stringent requirements of analog/RF SoCs and portable electronics.
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