机器学习在硬件设计可解释性中的应用：挑战与机遇
ML For Hardware Design Interpretability: Challenges and Opportunities
AI总结：
本文探讨硬件设计可解释性（尤其是RTL转自然语言任务）对设计效率的影响，回顾LLMs在该领域的应用现状，指出未解决的挑战并提出机遇，旨在指导相关研究以加速硬件设计流程。
摘要：
机器学习（ML）模型规模和复杂度的不断增长，推动了对能够高效支持ML工作负载的定制硬件加速器的需求。然而，此类加速器的设计仍是一个耗时的过程，严重依赖工程师通过清晰的文档和有效的沟通手动确保设计可解释性。大型语言模型（LLMs）的最新进展为自动化这些设计可解释性任务提供了广阔前景，尤其是为寄存器传输级（RTL）代码生成自然语言描述，即我们所说的“RTL转自然语言任务”。本文探讨了设计可解释性（尤其是在RTL转自然语言任务中）如何影响硬件设计流程的效率，回顾了现有将LLMs应用于这些任务的工作，强调了数据、计算和模型开发等方面尚未解决的关键挑战，并指出了应对这些挑战的机遇，旨在指导未来利用ML自动化RTL转自然语言任务、提升硬件设计可解释性的研究，从而加速硬件设计流程，满足机器学习及其他领域对定制硬件加速器日益增长的需求。
英文摘要：
The increasing size and complexity of machine learning (ML) models have driven the growing need for custom hardware accelerators capable of efficiently supporting ML workloads. However, the design of such accelerators remains a time-consuming process, heavily relying on engineers to manually ensure design interpretability through clear documentation and effective communication. Recent advances in large language models (LLMs) offer a promising opportunity to automate these design interpretability tasks, particularly the generation of natural language descriptions for register-transfer level (RTL) code, what we refer to as "RTL-to-NL tasks." In this paper, we examine how design interpretability, particularly in RTL-to-NL tasks, influences the efficiency of the hardware design process. We review existing work adapting LLMs for these tasks, highlight key challenges that remain unaddressed, including those related to data, computation, and model development, and identify opportunities to address them. By doing so, we aim to guide future research in leveraging ML to automate RTL-to-NL tasks and improve hardware design interpretability, thereby accelerating the hardware design process and meeting the increasing demand for custom hardware accelerators in machine learning and beyond.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
