比特世界建筑师：以真值表引导的掩码自回归建模用于电路生成
Architect of the Bits World: Masked Autoregressive Modeling for Circuit Generation Guided by Truth Table
AI总结：
本文提出CircuitVQ分词器与CircuitAR掩码自回归模型，结合可微架构搜索从真值表生成电路，解决了传统逻辑综合的次优问题和DAS的计算与优化难题。
摘要：
逻辑综合是电子设计自动化（EDA）中的关键阶段，它优化门级电路以最小化集成电路（ICs）的功耗和面积占用。传统逻辑综合工具依赖人工设计的启发式方法，往往产生次优结果。尽管可微架构搜索（DAS）在从真值表生成电路方面展现出潜力，但它面临计算复杂度高、收敛到局部最优以及大量超参数调优等挑战。因此，我们提出一种将条件生成模型与DAS相结合用于电路生成的新方法。我们的方法首先引入CircuitVQ，这是一个基于我们的Circuit AutoEncoder训练的电路分词器。随后我们开发了CircuitAR，这是一种利用CircuitVQ作为分词器的掩码自回归模型。CircuitAR能够从真值表生成初步电路结构，从而引导DAS产生功能等价的电路。值得注意的是，我们观察到CircuitAR模型在生成复杂电路结构方面具有可扩展性和涌现能力。大量实验也证明了我们方法的优越性能。这项研究弥合了概率生成模型与精确电路生成之间的差距，为逻辑综合提供了一种鲁棒的解决方案。
英文摘要：
Logic synthesis, a critical stage in electronic design automation (EDA), optimizes gate-level circuits to minimize power consumption and area occupancy in integrated circuits (ICs). Traditional logic synthesis tools rely on human-designed heuristics, often yielding suboptimal results. Although differentiable architecture search (DAS) has shown promise in generating circuits from truth tables, it faces challenges such as high computational complexity, convergence to local optima, and extensive hyperparameter tuning. Consequently, we propose a novel approach integrating conditional generative models with DAS for circuit generation. Our approach first introduces CircuitVQ, a circuit tokenizer trained based on our Circuit AutoEncoder We then develop CircuitAR, a masked autoregressive model leveraging CircuitVQ as the tokenizer. CircuitAR can generate preliminary circuit structures from truth tables, which guide DAS in producing functionally equivalent circuits. Notably, we observe the scalability and emergent capability in generating complex circuit structures of our CircuitAR models. Extensive experiments also show the superior performance of our method. This research bridges the gap between probabilistic generative models and precise circuit generation, offering a robust solution for logic synthesis.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
