利用含108500个Josephson结的交流偏置移位寄存器表征磁通俘获并制造大规模超导电路
Characterization of Flux Trapping in and Fabrication of Large-Scale Superconductor Circuits Using AC-Biased Shift Registers With 108500 Josephson Junctions
AI总结：
本文设计含108500个JJ的交流偏置SFQ移位寄存器，通过多轮冷却和30块芯片测试，表征磁通俘获、工艺良率与参数离散，确定GP临界间距并实现约每百万JJ一个缺陷的检测。
摘要：
为表征磁通俘获、制造工艺良率和参数离散，我们设计、制造并测试了多种超导集成电路；每块5 mm × 5 mm芯片包含6个交流供电的SFQ移位寄存器，总计27078 bit和108500个Josephson结（JJ）。电路中的6个4513 bit寄存器共用单相交流时钟，并具有独立的输入/输出驱动器，因此能够并行测试。我们研究了电路中的磁通俘获：这些电路在两个有源接地平面（GP）中采用不同几何形状、尺寸和moat间距，并可包含至多三个额外的“dummy”GP；测试经历了多次以不同冷却速率通过临界温度的冷却过程，残余磁场最高约1.2 μT。对于沿寄存器单元侧边排列的狭缝型和方形moat，我们发现隔离在moat中的磁通对寄存器工作裕量的影响可忽略，moat之外发生有害磁通俘获的概率也可忽略。采用宽度0.3 μm、占用电路面积不足2%的狭缝moat时，电路在100%的冷却过程中均可完全工作，这支持了VLSI超导数字电路的可行性。我们发现，在GP间距很近的电路中，moat之外的磁通俘获显著增强，并确定了GP之间的临界距离t_c=0.6 μm。当GP间距小于t_c时，电路在100%的冷却过程中均无法工作。我们测量了30块芯片，涉及超过300万个JJ，并测定了138个寄存器中的独立单元裕量，以表征与制造相关的参数离散并检测制造缺陷和磁通俘获事件。通过在独立单元裕量的统计分布中寻找离群单元，我们检测到约每百万个JJ一个缺陷，且在多数情况下，该缺陷会导致受影响单元中发生磁通俘获。
英文摘要：
A variety of superconductor integrated circuits comprising six ac-powered SFQ shift registers with a total of 27078 bits and 108500 Josephson junctions (JJs) per 5 mm x 5 mm chip have been designed, fabricated, and tested to characterize flux trapping, fabrication process yield, and parameter spread. The six 4513-bit registers in the circuits have a common single-phase ac clock and individual input/output drivers enabling their parallel testing. We have investigated flux trapping in the circuits with various geometry, size, and distance between moats in two active ground planes (GPs), and containing up to three additional 'dummy' GPs, using multiple cooldowns through the critical temperature with various cooling rates and residual magnetic fields up to ~1.2 $μ$T. For the slit-type and square moats arrayed along the sides of the register cells, we have found a negligible effect of flux sequestered in the moats on the operating margins of the registers, and negligible probability of detrimental flux trapping outside of the moats. Circuits with 0.3-$μ$m-wide slit moats occupying <2% of the circuit area were fully operational in 100% of cooldowns, supporting the viability of VLSI superconductor digital circuits. We have found a strong enhancement of flux trapping outside of the moats in circuits with closely spaced GPs and determined a critical distance, t$_c$=0.6 $μ$m, between them. The presence of GPs spaced below t$_c$ rendered the circuits nonoperational in 100% of cooldowns. We have measured 30 chips with >3M JJs and determined individual cell margins in 138 registers to characterize the fabrication-related parameter spread and detect fabrication defects and flux-trapping events. By finding outlier cells in the statistical distribution of the individual cell margins, we detected about one defect per million JJs, in most cases causing magnetic flux trapping in the affected cell.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
