Tempus Core：面向低精度边缘深度学习加速器的面积-功耗高效时间一元卷积核心
Tempus Core: Area-Power Efficient Temporal-Unary Convolution Core for Low-Precision Edge DLAs
AI总结：
本文提出 Tempus Core，一种基于时间-一元-二进制乘法器的高度可扩展卷积核心，可无缝集成到 NVDLA 中，在 INT8/INT4 精度下显著降低面积和功耗并提升等面积吞吐量，为边缘 AI 推理提供高效一元硬件方案。
摘要：
深度神经网络（DNN）日益增长的复杂性给边缘推理部署带来了重大挑战，原因是边缘设备存在资源和功耗约束。近期关于基于一元编码的矩阵乘法硬件研究旨在利用数据稀疏性和低精度数值来提升硬件效率。然而，由于处理单元（PE）阵列数据流存在差异，此类一元硬件在商用深度学习加速器（DLA）中的采用和集成仍然有限。本文提出了 Tempus Core，一种具有高度可扩展性的基于一元编码的 PE 阵列卷积核心，该阵列由 tub（时间-一元-二进制）乘法器组成，能够与 NVDLA（NVIDIA 用于加速 CNN 的开源 DLA）无缝集成，同时保持数据流兼容性并提升硬件效率。对不同数据通路粒度的分析表明，在 45nm CMOS 工艺下，对于 INT8 精度，Tempus Core 的 PE 单元（PCU）相较于 NVDLA 的 CMAC 单元，面积和功耗分别降低了 59.3% 和 15.3%。考虑 Tempus Core 中的 16x16 PE 阵列，面积和功耗分别改善了 75% 和 62%，同时在 INT8 和 INT4 精度下分别提供了 5 倍和 4 倍的等面积吞吐量提升。Tempus Core PCU 的布局布线后分析表明，在 45nm CMOS 工艺下，用于 INT4 精度的 16x4 PE 阵列仅需 0.017 mm² 的芯片面积，总功耗仅为 6.2mW。我们证明，面积-功耗高效的一元硬件可以无缝集成到传统 DLA 中，为面向边缘 AI 推理的高效一元硬件铺平了道路。
英文摘要：
The increasing complexity of deep neural networks (DNNs) poses significant challenges for edge inference deployment due to resource and power constraints of edge devices. Recent works on unary-based matrix multiplication hardware aim to leverage data sparsity and low-precision values to enhance hardware efficiency. However, the adoption and integration of such unary hardware into commercial deep learning accelerators (DLA) remain limited due to processing element (PE) array dataflow differences. This work presents Tempus Core, a convolution core with highly scalable unary-based PE array comprising of tub (temporal-unary-binary) multipliers that seamlessly integrates with the NVDLA (NVIDIA's open-source DLA for accelerating CNNs) while maintaining dataflow compliance and boosting hardware efficiency. Analysis across various datapath granularities shows that for INT8 precision in 45nm CMOS, Tempus Core's PE cell unit (PCU) yields 59.3% and 15.3% reductions in area and power consumption, respectively, over NVDLA's CMAC unit. Considering a 16x16 PE array in Tempus Core, area and power improves by 75% and 62%, respectively, while delivering 5x and 4x iso-area throughput improvements for INT8 and INT4 precisions. Post-place and route analysis of Tempus Core's PCU shows that the 16x4 PE array for INT4 precision in 45nm CMOS requires only 0.017 mm^2 die area and consumes only 6.2mW of total power. We demonstrate that area-power efficient unary-based hardware can be seamlessly integrated into conventional DLAs, paving the path for efficient unary hardware for edge AI inference.
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