基于关系图神经网络与强化学习的有效模拟集成电路布局规划
Effective Analog ICs Floorplanning with Relational Graph Neural Networks and Reinforcement Learning
AI总结：
本文提出结合关系图卷积神经网络与强化学习的模拟IC自动布局规划方法，实现跨电路设计知识迁移，在6个工业电路上较现有技术显著提升速度、面积与线长，并大幅缩短整体布局时间。
摘要：
模拟集成电路（IC）布局规划通常是一个手工过程，由版图工程师规划器件和模块的摆放位置。这一过程因布局规划与布线步骤之间的相互依赖、大量电气和版图相关约束，以及模拟设计中对高度定制化的期望而变得更加复杂。本文提出了一种基于强化学习的新型自动布局规划算法，并通过关系图卷积神经网络模型对其进行增强，用于编码电路特征和位置约束。这两种机器学习方法的结合使得知识能够在具有不同拓扑结构和约束的不同电路设计之间迁移，从而提高了方案的泛化能力。在6个工业电路上的应用表明，我们的方法在速度、面积和半周长线长方面均优于现有的布局规划技术。当集成到用于版图完成的过程化生成器中时，与手工布局相比，整体布局时间减少了67.3%，平均面积减少了8.3%。
英文摘要：
Analog integrated circuit (IC) floorplanning is typically a manual process with the placement of components (devices and modules) planned by a layout engineer. This process is further complicated by the interdependence of floorplanning and routing steps, numerous electric and layout-dependent constraints, as well as the high level of customization expected in analog design. This paper presents a novel automatic floorplanning algorithm based on reinforcement learning. It is augmented by a relational graph convolutional neural network model for encoding circuit features and positional constraints. The combination of these two machine learning methods enables knowledge transfer across different circuit designs with distinct topologies and constraints, increasing the \emph{generalization ability} of the solution. Applied to $6$ industrial circuits, our approach surpassed established floorplanning techniques in terms of speed, area and half-perimeter wire length. When integrated into a \emph{procedural generator} for layout completion, overall layout time was reduced by $67.3\%$ with a $8.3\%$ mean area reduction compared to manual layout.
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