LoopTree：探索融合层数据流加速器设计空间
LoopTree: Exploring the Fused-layer Dataflow Accelerator Design Space
AI总结：
本文提出更广泛的融合层数据流加速器设计空间、系统分类法和LoopTree评估模型，通过探索分块、数据保留与重计算组合，实现更高效设计，如缓冲区容量最多减少10倍。
摘要：
延迟和能耗是深度神经网络（DNN）加速器性能的关键指标。导致延迟和能耗的一个重要因素是数据传输。减少数据传输的一种方法是当多个操作使用相同数据时重用数据。融合层加速器通过将中间数据保留在片上缓冲区中来跨不同层的操作重用数据，这已被证明能降低能耗和延迟。此外，中间数据通常被分块（即分成小块）以减少重用数据所需的片上缓冲区容量。由于片上缓冲区容量通常比计算单元更受限，融合层数据流加速器也可能会重新计算中间数据的某些部分，而不是将其保留在缓冲区中。要在片上缓冲区容量、片外传输和重新计算之间实现高效的权衡，需要系统地探索融合层数据流设计空间。然而，先前的工作仅探索了设计空间的一个子集，更高效的设计尚未被探索。在这项工作中，我们提出了（1）一个更广泛的设计空间，在分块、数据保留、重新计算方面有更多选择，重要的是，允许我们将它们结合起来探索，（2）一个系统指定设计的分类法，以及（3）一个模型 LoopTree，用于评估该设计空间中设计的延迟、能耗、缓冲区容量需求和片外传输。我们针对一组具有代表性的先前架构验证了我们的模型，实现了最坏情况下4%的误差。最后，我们展示了案例研究，说明探索这个更大的空间如何产生更高效的设计（例如，为实现相同的片外传输，缓冲区容量最多减少10倍）。
英文摘要：
Latency and energy consumption are key metrics in the performance of deep neural network (DNN) accelerators. A significant factor contributing to latency and energy is data transfers. One method to reduce transfers or data is reusing data when multiple operations use the same data. Fused-layer accelerators reuse data across operations in different layers by retaining intermediate data in on-chip buffers, which has been shown to reduce energy consumption and latency. Moreover, the intermediate data is often tiled (i.e., broken into chunks) to reduce the on-chip buffer capacity required to reuse the data. Because on-chip buffer capacity is frequently more limited than computation units, fused-layer dataflow accelerators may also recompute certain parts of the intermediate data instead of retaining them in a buffer. Achieving efficient trade-offs between on-chip buffer capacity, off-chip transfers, and recomputation requires systematic exploration of the fused-layer dataflow design space. However, prior work only explored a subset of the design space, and more efficient designs are left unexplored. In this work, we propose (1) a more extensive design space that has more choices in terms of tiling, data retention, recomputation and, importantly, allows us to explore them in combination, (2) a taxonomy to systematically specify designs, and (3) a model, LoopTree, to evaluate the latency, energy consumption, buffer capacity requirements, and off-chip transfers of designs in this design space. We validate our model against a representative set of prior architectures, achieving a worst-case 4% error. Finally, we present case studies that show how exploring this larger space results in more efficient designs (e.g., up to a 10$\times$ buffer capacity reduction to achieve the same off-chip transfers).
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