面向 Lempel-Ziv 4 压缩算法的高吞吐量硬件加速器
A High-Throughput Hardware Accelerator for Lempel-Ziv 4 Compression Algorithm
AI总结：
本文提出一种LZ4硬件加速器，通过限制并行窗口为单一匹配并消除反馈回路，实现16.10 Gb/s吞吐量，较现有技术提升2.648倍，压缩比仅降低4.93%-11.68%。
摘要：
本文深入探讨了 Lempel-Ziv 4 (LZ4) 算法的最新硬件实现，指出了限制单内核压缩器吞吐量的两个关键因素。首先，单内核设计中所展现的实际并行度未达到理论潜力。其次，由于反馈回路的存在，时钟频率受到限制。为应对这些挑战，我们提出了一种新颖方案，将每个并行化窗口限制为单一匹配，从而提升实际并行度。此外，通过限制最大匹配长度，我们消除了架构内的反馈回路，使吞吐量得以显著提升。最后，我们提出了一种高速硬件架构。实现结果表明，所提出的架构实现了高达 16.10 Gb/s 的吞吐量，相较于现有最先进技术提升了 2.648 倍。与 GitHub 上公开的官方软件实现所达到的 LZ4 压缩比相比，新设计在采用不同哈希表条目数时，仅导致压缩比可接受的降低，范围在 4.93% 至 11.68% 之间。
英文摘要：
This paper delves into recent hardware implementations of the Lempel-Ziv 4 (LZ4) algorithm, highlighting two key factors that limit the throughput of single-kernel compressors. Firstly, the actual parallelism exhibited in single-kernel designs falls short of the theoretical potential. Secondly, the clock frequency is constrained due to the presence of the feedback loops. To tackle these challenges, we propose a novel scheme that restricts each parallelization window to a single match, thus elevating the level of actual parallelism. Furthermore, by restricting the maximum match length, we eliminate the feedback loops within the architecture, enabling a significant boost in throughput. Finally, we present a high-speed hardware architecture. The implementation results demonstrate that the proposed architecture achieves a throughput of up to 16.10 Gb/s, exhibiting a 2.648x improvement over the start-of-the-art. The new design only results in an acceptable compression ratio reduction ranging from 4.93% to 11.68% with various numbers of hash table entries, compared to the LZ4 compression ratio achieved by official software implementations disclosed on GitHub.
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