克服代工厂碳纳米管晶体管中的环境漂移与负偏压温度不稳定性
Overcoming Ambient Drift and Negative-Bias Temperature Instability in Foundry Carbon Nanotube Transistors
AI总结：
针对代工厂碳纳米管晶体管（CNFET）缺乏环境漂移与负偏压温度不稳定性（NBTI）全面研究的问题，首次通过氮化硅封装和交流/脉冲操作分别大幅降低环境漂移、延长NBTI失效时间，为其可靠性提升提供关键技术方案。
摘要：
后端工艺（BEOL）逻辑集成正成为补充前端工艺（FEOL）硅技术的互补性缩放路径。在BEOL逻辑的多种选项中，碳纳米管场效应晶体管（CNFET）已在商业硅代工厂中实现集成，且复杂CNFET电路（如RISC-V内核、SRAM阵列）已得到演示。然而，目前缺乏分析CNFET环境漂移（即空气稳定性）和可靠性的全面研究。本文首次通过以下技术对CNFET的环境漂移和负偏压温度不稳定性（NBTI）进行了全面表征并展示了克服方法：（1）氮化硅封装可限制环境大气引起的阈值电压漂移（90天内中位VT漂移降低约8倍）；（2）交流/脉冲操作在宽频率范围内相比直流操作显著改善CNFET的NBTI（例如，在125℃、栅极应力偏置VGS,stress=-1.2V且目标VT漂移容差<100mV的条件下，10MHz、20%占空比的交流操作可将CNFET的NBTI失效时间延长>10000倍）。
英文摘要：
Back-end-of-line (BEOL) logic integration is emerging as a complementary scaling path to supplement front-end-of-line (FEOL) Silicon. Among various options for BEOL logic, Carbon Nanotube Field-Effect Transistors (CNFETs) have been integrated within commercial silicon foundries, and complex CNFET circuits (e.g., RISC-V core, SRAM arrays) have been demonstrated. However, there lacks comprehensive studies that analyze the ambient drift (i.e., air-stability) and reliability of CNFETs. Here, for the first time, we thoroughly characterize and demonstrate how to overcome ambient drift and negative bias temperature instability (NBTI) in CNFETs using the following techniques: (1) Silicon Nitride encapsulation to limit ambient atmosphere induced threshold voltage shift (~8x reduction of median VT shift over 90 days) and (2) AC/pulsed operation to significantly improve CNFET NBTI vs. DC operation across a wide frequency range (e.g., 20% duty cycle AC operation at 10 MHz could extend CNFET NBTI time-to-failure by >10000x vs. DC for a target VT shift tolerance < 100 mV with gate stress bias VGS,stress = -1.2 V at 125 C).
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
