重新思考针对快速设备、廉价核心与一致性互连的可编程I/O
Rethinking Programmed I/O for Fast Devices, Cheap Cores, and Coherent Interconnects
AI总结：
本文质疑基于DMA的I/O模型，提出利用缓存一致性互连（如CXL3.0）的可编程I/O，在真实硬件上实现低延迟、高吞吐，并展示三个用例验证其优势。
摘要：
传统观点认为，CPU上运行的操作系统与高带宽I/O设备之间的高效接口应使用直接内存访问（DMA）来卸载数据传输，使用描述符环进行缓冲和排队，并使用中断实现核心与设备之间的异步。本文基于两个趋势质疑这一观点：现代和新兴的缓存一致性互连（如CXL3.0），以及工作负载，特别是微服务和无服务器计算。与之前的一些研究一样，我们认为基于DMA的模型的假设已经过时，在许多用例中，可编程I/O（即CPU通过加载和存储指令显式地向设备传输数据和从设备传输控制信息）能提供更高效的系统。然而，我们将这一想法推得更远。我们在真实硬件实现中展示了，使用一种开放的缓存一致性协议（该协议将缓存状态转换暴露给智能设备），可以实现细粒度通信的延迟收益，并且吞吐量与基于现代互连的DMA相当。我们还演示了三个用例：在加速器上细粒度RPC风格的函数调用、流式数据流引擎中算子的卸载，以及面向无服务器函数的网络接口，将我们对一致性的使用与传统的DMA风格交互以及基于PCIe的内存映射可编程I/O的高度优化实现进行了比较。
英文摘要：
Conventional wisdom holds that an efficient interface between an OS running on a CPU and a high-bandwidth I/O device should use Direct Memory Access (DMA) to offload data transfer, descriptor rings for buffering and queuing, and interrupts for asynchrony between cores and device. In this paper we question this wisdom in the light of two trends: modern and emerging cache-coherent interconnects like CXL3.0, and workloads, particularly microservices and serverless computing. Like some others before us, we argue that the assumptions of the DMA-based model are obsolete, and in many use-cases programmed I/O, where the CPU explicitly transfers data and control information to and from a device via loads and stores, delivers a more efficient system. However, we push this idea much further. We show, in a real hardware implementation, the gains in latency for fine-grained communication achievable using an open cache-coherence protocol which exposes cache transitions to a smart device, and that throughput is competitive with DMA over modern interconnects. We also demonstrate three use-cases: fine-grained RPC-style invocation of functions on an accelerator, offloading of operators in a streaming dataflow engine, and a network interface targeting serverless functions, comparing our use of coherence with both traditional DMA-style interaction and a highly-optimized implementation using memory-mapped programmed I/O over PCIe.
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