为匿名网络流量图挑战高速提取TCPIP报头
Extracting TCPIP Headers at High Speed for the Anonymized Network Traffic Graph Challenge
AI总结：
针对网络流量处理需求，本文结合P4语言与高级综合（HLS）在最新AMD FPGA上实现基于FPGA的智能网卡，可高效提取源-目的IP地址构建匿名流量矩阵，处理速率达约95 Gbps，能匹配100 Gbps网络流量。
摘要：
现场可编程门阵列（FPGA）因其灵活性和效率，在计算密集型网络处理中发挥重要作用。特别是借助P4网络编程模型的高级抽象，FPGA在数据包处理方面展现出强大潜力。通过FPGA处理支持P4语言，网络研究人员可创建定制化的FPGA网络功能，并在直接连接网络的加速器上执行网络任务。P4语言的一个特点是无状态；但本研究中的FPGA实现需要状态信息。这通过P4外部模块（externs）描述设计的有状态部分，并使用高级综合（HLS）在FPGA上实现。本文展示使用基于FPGA的智能网卡（SmartNIC）从网络数据包高效提取源-目的IP地址信息，构建匿名网络流量矩阵以供进一步分析。该实现是在最新AMD FPGA上结合P4与HLS开发网络功能的首个实例。我们的设计通过P4与高级综合的结合实现约95 Gbps的处理速率，能够跟上直接从网络接收的100 Gbps流量。
英文摘要：
Field Programmable Gate Arrays (FPGAs) play a significant role in computationally intensive network processing due to their flexibility and efficiency. Particularly with the high-level abstraction of the P4 network programming model, FPGA shows a powerful potential for packet processing. By supporting the P4 language with FPGA processing, network researchers can create customized FPGA-based network functions and execute network tasks on accelerators directly connected to the network. A feature of the P4 language is that it is stateless; however, the FPGA implementation in this research requires state information. This is accomplished using P4 externs to describe the stateful portions of the design and to implement them on the FPGA using High-Level Synthesis (HLS). This paper demonstrates using an FPGA-based SmartNIC to efficiently extract source-destination IP address information from network packets and construct anonymized network traffic matrices for further analysis. The implementation is the first example of the combination of using P4 and HLS in developing network functions on the latest AMD FPGAs. Our design achieves a processing rate of approximately 95 Gbps with the combined use of P4 and High-level Synthesis and is able to keep up with 100 Gbps traffic received directly from the network.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
