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arXiv 2409.07069eess.SP
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面向5G/6G相控阵接收机的22nm FDSOI CMOS工艺亚毫瓦级30GHz VG-LNA的基准测试与验证

Benchmarking and Validation of Sub-mW 30GHz VG-LNAs in 22nm FDSOI CMOS for 5G/6G Phased-Array Receivers

Domenico Zito, Michele Spasaro

AI总结:

本研究针对5G/6G相控阵接收机需求,在22nm FDSOI CMOS工艺下对两款30GHz低功耗VG-LNA开展基准测试,验证了其设计方法可实现低功耗小尺寸且达标的性能。

摘要:

下一代(5G/6G)无线系统需要低功耗毫米波相控阵集成电路。可变增益低噪声放大器(VGLNA,Variable-gain LNAs)是降低硬件复杂度、提升性能并扩展功能的关键构建模块。本文针对两款用于相控阵集成电路的低功耗30GHz VG-LNA开展性能基准测试,两款器件可为30GHz 8×8天线阵列中18dB泰勒锥度提供7.5dB的增益控制,旨在全面验证这类新型VGLNA及其设计方法。具体而言,本文报道了第二款实现方案(VG-LNA2),相较于采用6个增益控制背栅电压和常规阈值电压MOSFET的首款实现方案(VG-LNA1),VG-LNA2采用更少的(4个)增益控制背栅电压以及超低阈值电压MOSFET,二者均基于相同的22nm FDSOI CMOS工艺制造。结果表明,VG-LNA2的性能与VG-LNA1相当,且功耗略低。总体而言,性能基准测试显示,这类新型VGLNA采用的设计方法可实现创纪录的低功耗和小尺寸方案,且能达到目标性能,不受增益控制背栅电压排布和晶体管组的影响,从而全面验证了该创新设计特性和有效设计方法的可行性。

英文摘要:

Next-generation (5G/6G) wireless systems demand low-power mm-wave phased-array ICs. Variable-gain LNAs (VGLNAs) are key building blocks enabling hardware complexity reduction, performance enhancement and functionality extension. This paper reports a performance benchmarking of two low-power 30GHz VG-LNAs for phased-array ICs, which provide a 7.5dB gain control for 18dB Taylor taper in a 30GHz 8x8 antenna array, for a comprehensive validation of the new class of VGLNAs and its design methodology. In particular, this paper reports a second and implementation (VG-LNA2) with a reduced number (four) of gain-control back-gate voltages and super-low-Vt MOSFETs, with respect to the previous first implementation (VG-LNA1) with six gain-control back-gate voltages and regular- Vt MOSFETs, both in the same 22nm FDSOI CMOS technology. The results show that VG-LNA2 exhibits performance comparable to those of VG-LNA1, with a slightly lower power consumption. Overall, the performance benchmarking shows that the design methodology adopted for the new class of VG-LNAs leads to record low-power consumption and small form factor solutions reaching the targeted performances, regardless of the arrangements of the back-gate voltages for gain control and transistor sets, resulting in a comprehensive validation of the innovative design features and effective design methodology.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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