挑战可移植性范式：使用SYCL与OpenCL进行FPGA加速
Challenging Portability Paradigms: FPGA Acceleration Using SYCL and OpenCL
AI总结：
本文评估了SYCL与OpenCL在FPGA上移植高度并行应用时的性能可移植性，发现未经FPGA定制优化时ND-range内核显著优于单任务内核，挑战了传统开发建议。
摘要：
随着人们对面向HPC应用的基于FPGA的加速器兴趣日益增长，新的挑战也随之出现，尤其是在不同的编程和可移植性问题方面。本文旨在提供当前FPGA工具链状况及其问题的概览。为此，我们评估了两个用于开发HPC FPGA解决方案的框架（SYCL和OpenCL）的性能可移植性，使用它们将一个高度并行的应用移植到FPGA上，同时使用ND-range和单任务两种类型的内核。开发者在使用FPGA时的普遍建议是为其开发单任务内核，因为这类内核通常被认为更适合此类硬件。然而，我们发现，当使用OpenCL和SYCL等高级方法对一个高度并行的应用进行编程且不进行针对FPGA的定制优化时，ND-range内核显著优于单任务代码。具体而言，虽然SYCL在生成以单任务代码描述的应用的高效FPGA实现方面存在困难，但其在ND-range内核下的性能表现出色，这一结果出人意料地有利。
英文摘要：
As the interest in FPGA-based accelerators for HPC applications increases, new challenges also arise, especially concerning different programming and portability issues. This paper aims to provide a snapshot of the current state of the FPGA tooling and its problems. To do so, we evaluate the performance portability of two frameworks for developing FPGA solutions for HPC (SYCL and OpenCL) when using them to port a highly-parallel application to FPGAs, using both ND-range and single-task type of kernels. The developer's general recommendation when using FPGAs is to develop single-task kernels for them, as they are commonly regarded as more suited for such hardware. However, we discovered that, when using high-level approaches such as OpenCL and SYCL to program a highly-parallel application with no FPGA-tailored optimizations, ND-range kernels significantly outperform single-task codes. Specifically, while SYCL struggles to produce efficient FPGA implementations of applications described as single-task codes, its performance excels with ND-range kernels, a result that was unexpectedly favorable.
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