ResiLogic：利用可组合性和多样性设计抗故障与抗入侵芯片
ResiLogic: Leveraging Composability and Diversity to Design Fault and Intrusion Resilient Chips
AI总结：
针对供应链部分利益相关者不可信的威胁模型，提出ResiLogic框架，通过“可组合性实现多样性”构建电路，提升抗三类攻击能力五倍，并展示E-Graphs生成多样化电路的应用。
摘要：
设计抗故障和毛刺的芯片是一项长期挑战。过去已采用细粒度门级多样性和粗粒度模块化冗余方法，但这些方法在供应链中部分利益相关者不可信的其他威胁模型下未得到充分研究。数字主权紧张局势加剧，引发了对使用外国现成工具、IP或外包制造的担忧，推动了该威胁模型下抗干扰芯片设计的研究。本文针对一种威胁模型，该模型考虑了三种与抗干扰相关的攻击：分布式攻击、区域攻击和复合攻击。为缓解这些攻击，我们引入ResiLogic框架，该框架利用“通过可组合性实现多样性”：通过设计构建由较小的多样化电路组成的多样化电路。这使设计人员能够在设计时创建电路，而无需额外的空间或成本冗余。在不同粒度级别使用此方法，可将ResiLogic中电路设计对三种考虑攻击的抗干扰能力提高五倍。此外，我们还展示了如何利用E-Graphs在给定重写规则下生成多样化电路。
英文摘要：
A long-standing challenge is the design of chips resilient to faults and glitches. Both fine-grained gate diversity and coarse-grained modular redundancy have been used in the past. However, these approaches have not been well-studied under other threat models where some stakeholders in the supply chain are untrusted. Increasing digital sovereignty tensions raise concerns regarding the use of foreign off-the-shelf tools and IPs, or off-sourcing fabrication, driving research into the design of resilient chips under this threat model. This paper addresses a threat model considering three pertinent attacks to resilience: distribution, zonal, and compound attacks. To mitigate these attacks, we introduce the \texttt{ResiLogic} framework that exploits \textit{Diversity by Composability}: constructing diverse circuits composed of smaller diverse ones by design. This gives designer the capability to create circuits at design time without requiring extra redundancy in space or cost. Using this approach at different levels of granularity is shown to improve the resilience of circuit design in \texttt{ResiLogic} against the three considered attacks by a factor of five. Additionally, we also make a case to show how E-Graphs can be utilized to generate diverse circuits under given rewrite rules.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
