arXivDaily arXiv每日学术速递 周一至周五更新
arXiv 2409.01348cs.CVcs.CEcs.LG
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PatternPaint:使用基于扩散的修复进行实用版图图案生成

PatternPaint: Practical Layout Pattern Generation Using Diffusion-Based Inpainting

Dept. of Electrical & Computer Engineering, Duke University(杜克大学电气与计算机工程系);Intel Corporation(英特尔公司);Dept. of Electrical & Computer Engineering, TAMU, College Station(塔拉斯大学电气与计算机工程系)

Guanglei Zhou, Bhargav Korrapati, Gaurav Rajavendra Reddy, Chen-Chia Chang, Jingyu Pan, Jiang Hu, Yiran Chen, Dipto G. Thakurta

AI总结:

针对新工艺节点版图数据稀缺问题,提出基于扩散模型的PatternPaint框架,通过模板去噪和少样本微调,在Intel 18A节点下实现高合法率和高多样性的2D金属互连版图生成。

摘要:

生成多样化的VLSI版图图案对于制造设计中的各种下游任务至关重要,因为设计规则在新工艺节点的开发过程中不断演变。然而,现有的基于训练的版图图案生成方法依赖于大型数据集。在实际场景中,尤其是在开发新工艺节点时,获取如此大量的版图数据具有挑战性。因此,使用大型数据集训练模型变得不切实际,限制了先前方法的可扩展性和适应性。为此,我们提出了PatternPaint,这是一个基于扩散的框架,能够在设计规则合规的训练样本有限的情况下生成合法图案。PatternPaint利用基于模板的去噪方案,将复杂的版图图案生成简化为一系列修复过程。此外,我们仅使用20个设计规则合规样本,对预训练的图像基础模型进行了少样本微调。实验结果表明,使用3nm以下工艺节点(Intel 18A),我们的模型是所有先前工作中唯一能够在复杂2D金属互连设计规则设置下生成合法图案的模型,并获得了高多样性得分。此外,与原始预训练模型相比,我们的少样本微调可将合法率提升1.87倍。因此,我们展示了一种用于开发新工艺节点时版图图案生成的即用型方法。

英文摘要:

Generating diverse VLSI layout patterns is essential for various downstream tasks in design for manufacturing, as design rules continually evolve during the development of new technology nodes. However, existing training-based methods for layout pattern generation rely on large datasets. In practical scenarios, especially when developing a new technology node, obtaining such extensive layout data is challenging. Consequently, training models with large datasets becomes impractical, limiting the scalability and adaptability of prior approaches. To this end, we propose PatternPaint, a diffusion-based framework capable of generating legal patterns with limited design-rule-compliant training samples. PatternPaint simplifies complex layout pattern generation into a series of inpainting processes with a template-based denoising scheme. Furthermore, we perform few-shot finetuning on a pretrained image foundation model with only 20 design-rule-compliant samples. Experimental results show that using a sub-3nm technology node (Intel 18A), our model is the only one that can generate legal patterns in complex 2D metal interconnect design rule settings among all previous works and achieves a high diversity score. Additionally, our few-shot finetuning can boost the legality rate with 1.87X improvement compared to the original pretrained model. As a result, we demonstrate a production-ready approach for layout pattern generation in developing new technology nodes.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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