用于保持精度的稀疏柱基嵌入式3D目标检测的选择性扩张卷积
Selectively Dilated Convolution for Accuracy-Preserving Sparse Pillar-based Embedded 3D Object Detection
AI总结：
针对稀疏柱体卷积因细粒度空间信息流受限导致精度下降的问题，提出选择性扩张卷积（SD-Conv）与加速器增强设计SPADE+，在保持检测精度的同时实现了最高18.1倍计算节省和16.2倍加速。
摘要：
柱基3D目标检测因通过人工密集化柱体以实现GPU友好处理所带来的速度和精度优势，在自动驾驶技术中获得了广泛关注。然而，密集柱体处理从根本上浪费了计算资源，因为它忽略了源自散乱点云数据的柱体固有稀疏性。受近期支持原生稀疏性的嵌入式加速器的启发，诸如子流形卷积（SubM-Conv）等稀疏柱体卷积方法旨在通过仅对活跃柱体应用卷积来减少这些冗余计算，但却遭受了显著的精度损失。我们的研究指出，这种精度损失归因于稀疏柱体网络中SubM-Conv受限的细粒度空间信息流（fSIF）。为克服这一限制，我们提出了一种选择性扩张卷积（SD-Conv），它评估已编码柱体的重要性并选择性地扩张卷积输出，从而增强关键柱体的感受野并提高目标检测精度。为了利用这种新颖的卷积方法实现实际加速，我们设计了SPADE+，作为对现有嵌入式稀疏卷积加速器的高效补充。该设计支持SD-Conv，且对面积和SRAM大小没有显著需求，实现了加速与模型精度之间的卓越权衡。这一战略性增强使我们的方法能够实现极致的柱体稀疏性，在不牺牲目标检测精度的前提下，在嵌入式加速器上带来了高达18.1倍的计算节省和16.2倍的加速。
英文摘要：
Pillar-based 3D object detection has gained traction in self-driving technology due to its speed and accuracy facilitated by the artificial densification of pillars for GPU-friendly processing. However, dense pillar processing fundamentally wastes computation since it ignores the inherent sparsity of pillars derived from scattered point cloud data. Motivated by recent embedded accelerators with native sparsity support, sparse pillar convolution methods like submanifold convolution (SubM-Conv) aimed to reduce these redundant computations by applying convolution only on active pillars but suffered considerable accuracy loss. Our research identifies that this accuracy loss is due to the restricted fine-grained spatial information flow (fSIF) of SubM-Conv in sparse pillar networks. To overcome this restriction, we propose a selectively dilated (SD-Conv) convolution that evaluates the importance of encoded pillars and selectively dilates the convolution output, enhancing the receptive field for critical pillars and improving object detection accuracy. To facilitate actual acceleration with this novel convolution approach, we designed SPADE+ as a cost-efficient augmentation to existing embedded sparse convolution accelerators. This design supports the SD-Conv without significant demands in area and SRAM size, realizing superior trade-off between the speedup and model accuracy. This strategic enhancement allows our method to achieve extreme pillar sparsity, leading to up to 18.1x computational savings and 16.2x speedup on the embedded accelerators, without compromising object detection accuracy.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
