一种面向Kyber的硬件友好型抗侧信道攻击洗牌对策
A Hardware-Friendly Shuffling Countermeasure Against Side-Channel Attacks for Kyber
AI总结：
针对Kyber抗量子密钥封装方案的侧信道攻击威胁，本文提出一种硬件友好型Fisher-Yates洗牌架构，在FPGA上以仅8.7%的效率损失显著提升安全性，优于现有硬件隐藏方案。
摘要：
CRYSTALS-Kyber已被NIST标准化为唯一能够抵御大规模量子计算机攻击的密钥封装机制（KEM）方案。然而，在即将到来的迁移过程中，仍需充分考虑其实现上的侧信道攻击（SCAs）问题。在本简报中，我们通过引入一种新颖的紧凑洗牌架构，提出了一种安全高效的Kyber硬件实现。首先，我们对Fisher-Yates洗牌算法进行了修改，使其更加硬件友好。随后，我们为知名的开源Kyber硬件实现设计了一种优化的洗牌架构，以增强所有已知及潜在侧信道泄漏点的安全性。最后，我们在FPGA上实现了修改后的Kyber设计，并评估了其安全性与性能。安全性通过在硬件上执行相关功耗分析（CPA）和测试向量泄漏评估（TVLA）进行验证。同时，FPGA布局布线结果表明，与原始未受保护版本相比，所提设计的硬件效率仅下降8.7%，远优于现有的硬件隐藏方案。
英文摘要：
CRYSTALS-Kyber has been standardized as the only key-encapsulation mechanism (KEM) scheme by NIST to withstand attacks by large-scale quantum computers. However, the side-channel attacks (SCAs) on its implementation are still needed to be well considered for the upcoming migration. In this brief, we propose a secure and efficient hardware implementation for Kyber by incorporating a novel compact shuffling architecture. First of all, we modify the Fisher-Yates shuffle to make it more hardware-friendly. We then design an optimized shuffling architecture for the well-known open-source Kyber hardware implementation to enhance the security of all known and potential side-channel leakage points. Finally, we implement the modified Kyber design on FPGA and evaluate its security and performance. The security is verified by conducting correlation power analysis (CPA) and test vector leakage assessment (TVLA) on the hardware. Meanwhile, FPGA place-and-route results show that the proposed design reports only 8.7% degradation on the hardware efficiency compared with the original unprotected version, much better than existing hardware hiding schemes.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
