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arXiv 2406.09535cs.LGcs.AR
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CircuitVAE:高效且可扩展的隐式电路优化

CircuitVAE: Efficient and Scalable Latent Circuit Optimization

NVIDIA(英伟达);Harmonic(哈蒙尼克公司);Hippocratic AI(希波克拉底人工智能公司)

Jialin Song, Aidan Swope, Robert Kirby, Rajarshi Roy, Saad Godil, Jonathan Raiman, Bryan Catanzaro

AI总结:

CircuitVAE将电路计算图嵌入连续空间并通过梯度下降优化仿真代理,以高样本效率设计大规模数字电路,在64位加法器上以不到一半样本预算超越强化学习和遗传算法,并能在真实芯片中超越商业工具。

摘要:

自动设计快速且节省空间的数字电路具有挑战性,因为电路是离散的,必须精确实现所需逻辑,并且仿真成本高昂。我们通过CircuitVAE应对这些挑战,CircuitVAE是一种搜索算法,它将计算图嵌入到连续空间中,并通过梯度下降优化物理仿真学习得到的代理模型。通过仔细控制仿真代理的过拟合并确保多样化探索,我们的算法具有很高的样本效率,同时能够优雅地扩展到大规模问题实例和高样本预算。我们通过设计跨越大范围尺寸、IO时序约束和样本预算的二进制加法器来测试CircuitVAE。我们的方法在设计大型电路方面表现出色,而其他算法在这些方面存在困难:与强化学习和遗传算法相比,CircuitVAE通常能用不到一半的样本预算找到更小且更快的64位加法器。我们还发现CircuitVAE可以在真实芯片中设计出最先进的加法器,证明我们的方法在现实环境中能够超越商业工具。

英文摘要:

Automatically designing fast and space-efficient digital circuits is challenging because circuits are discrete, must exactly implement the desired logic, and are costly to simulate. We address these challenges with CircuitVAE, a search algorithm that embeds computation graphs in a continuous space and optimizes a learned surrogate of physical simulation by gradient descent. By carefully controlling overfitting of the simulation surrogate and ensuring diverse exploration, our algorithm is highly sample-efficient, yet gracefully scales to large problem instances and high sample budgets. We test CircuitVAE by designing binary adders across a large range of sizes, IO timing constraints, and sample budgets. Our method excels at designing large circuits, where other algorithms struggle: compared to reinforcement learning and genetic algorithms, CircuitVAE typically finds 64-bit adders which are smaller and faster using less than half the sample budget. We also find CircuitVAE can design state-of-the-art adders in a real-world chip, demonstrating that our method can outperform commercial tools in a realistic setting.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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