面向低时延和抖动容忍工业物联网通信的OFDM标准兼容SC-NOFS波形
OFDM-Standard Compatible SC-NOFS Waveforms for Low-Latency and Jitter-Tolerance Industrial IoT Communications
AI总结：
本文提出不规则Sinc成形与单载波非正交频率成形波形，兼容5G标准，在工业物联网中实现18%时序资源节省，以降低时延并提升抖动容忍能力。
摘要：
传统通信侧重于规则且正交的信号波形，以简化信号处理并提高频谱效率。相比之下，下一代通信将致力于不规则且非正交的信号波形，以引入新的能力。本工作提出了一种频谱高效的不规则Sinc（irSinc）成形技术，重新审视了可追溯至1924年的传统Sinc，旨在提升工业物联网（IIoT）中的性能。在对时间要求严苛的IIoT应用中，低时延和时间抖动容忍是两个关键因素，它们显著影响性能和可靠性。认识到实际中时延和抖动的不可避免性，本工作旨在提出一种波形技术，通过降低时延并增强系统在时间抖动影响下的鲁棒性来缓解这些影响。irSinc的利用产生的信号在不牺牲误码性能的情况下提高了频谱效率。将irSinc集成到一个两阶段框架中，开发了一种单载波非正交频率成形（SC-NOFS）波形，展示了与5G标准的完美兼容性，使irSinc能够直接集成到现有的工业物联网设置中。通过5G标准信号配置，我们的信号在相同频谱带宽内实现了更快的数据传输。硬件实验验证了18%的时序资源节省，从而实现了降低时延或增强抖动容忍。
英文摘要：
Traditional communications focus on regular and orthogonal signal waveforms for simplified signal processing and improved spectral efficiency. In contrast, the next-generation communications would aim for irregular and non-orthogonal signal waveforms to introduce new capabilities. This work proposes a spectrally efficient irregular Sinc (irSinc) shaping technique, revisiting the traditional Sinc back to 1924, with the aim of enhancing performance in industrial Internet of things (IIoT). In time-critical IIoT applications, low-latency and time-jitter tolerance are two critical factors that significantly impact the performance and reliability. Recognizing the inevitability of latency and jitter in practice, this work aims to propose a waveform technique to mitigate these effects via reducing latency and enhancing the system robustness under time jitter effects. The utilization of irSinc yields a signal with increased spectral efficiency without sacrificing error performance. Integrating the irSinc in a two-stage framework, a single-carrier non-orthogonal frequency shaping (SC-NOFS) waveform is developed, showcasing perfect compatibility with 5G standards, enabling the direct integration of irSinc in existing industrial IoT setups. Through 5G standard signal configuration, our signal achieves faster data transmission within the same spectral bandwidth. Hardware experiments validate an 18% saving in timing resources, leading to either reduced latency or enhanced jitter tolerance.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
