面向边缘AI计算的一种0.96pJ/SOP、30.23K-neuron/mm^2的具有富勒烯状互连拓扑的异构类脑芯片
A 0.96pJ/SOP, 30.23K-neuron/mm^2 Heterogeneous Neuromorphic Chip With Fullerene-like Interconnection Topology for Edge-AI Computing
AI总结：
提出一种0.96 pJ/SOP的异构类脑SoC，采用富勒烯状互连拓扑和稀疏计算等技术，在55nm CMOS下实现高神经元密度和低功耗，有效应用于边缘AI计算。
摘要：
边缘AI计算要求高能效、低功耗以及相对较高的灵活性和紧凑的面积，这对AI芯片设计提出了挑战。本研究提出了一种0.96 pJ/SOP的异构类脑系统级芯片（SoC），具有富勒烯状互连拓扑，用于边缘AI计算。类脑核心集成了不同技术以提升计算能效，包括稀疏计算、部分膜电位更新和非均匀权重量化。多个类脑核心和多模态路由器构成了富勒烯状片上网络（NoC）。通信节点的平均度数比传统拓扑高32%，最小度方差为0.93，可实现先进的去中心化片上通信。此外，NoC可通过扩展片外高级路由节点进行扩展。RISC-V CPU和类脑处理器紧密耦合，在55nm CMOS工艺下制造于5.42 mm^2的裸片面积内。芯片具有0.52 mW/mm^2的低功率密度，相比相关工作降低了67.5%，并实现了30.23 K/mm^2的高神经元密度。最终，该芯片在不同数据集上被证明有效，并实现了0.96 pJ/SOP的能效。
英文摘要：
Edge-AI computing requires high energy efficiency, low power consumption, and relatively high flexibility and compact area, challenging the AI-chip design. This work presents a 0.96 pJ/SOP heterogeneous neuromorphic system-on-chip (SoC) with fullerene-like interconnection topology for edge-AI computing. The neuromorphic core integrates different technologies to augment computing energy efficiency, including sparse computing, partial membrane potential updates, and non-uniform weight quantization. Multiple neuromorphic cores and multi-mode routers form a fullerene-like network-on-chip (NoC). The average degree of communication nodes exceeds traditional topologies by 32%, with a minimal degree variance of 0.93, allowing advanced decentralized on-chip communication. Additionally, the NoC can be scaled up through extended off-chip high-level router nodes. A RISC-V CPU and a neuromorphic processor are tightly coupled and fabricated within a 5.42 mm^2 die area under 55 nm CMOS technology. The chip has a low power density of 0.52 mW/mm^2, reducing 67.5% compared to related works, and achieves a high neuron density of 30.23 K/mm^2. Eventually, the chip is demonstrated to be effective on different datasets and achieves 0.96 pJ/SOP energy efficiency.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
