增强ASIC技术映射的并行超级门计算
Enhancing ASIC Technology Mapping via Parallel Supergate Computing
AI总结：
本文提出一种并行超级门计算方法，利用输入受限模式并行生成候选并筛选，在32线程下实现4倍加速和10.1延迟缩减，有效平衡ASIC技术映射中的计算时间与延迟优化。
摘要：
随着大规模集成电路的发展，电子设计自动化（EDA）工具越来越注重效率，并行算法已成为一种趋势。延迟缩减的优化是ASIC技术映射的关键因素，而超级门技术在EDA工具流程中被证明是实现这一目标的有效方法。然而，我们观察到，增加生成的超级门数量可以减少延迟，但这以计算时间呈指数级增长为代价。在本文中，我们提出了一种并行超级门计算方法，以解决耗时与延迟优化之间的权衡问题。所提出的方法利用输入受限的超级门模式并行生成超级门候选，然后筛选出有效的超级门作为结果。实验结果表明了所提出方法的有效性，例如，在32线程下，它可以实现计算时间4倍加速和10.1的延迟缩减改进。
英文摘要：
With the development of large-scale integrated circuits, electronic design automation~(EDA) tools are increasingly emphasizing efficiency, with parallel algorithms becoming a trend. The optimization of delay reduction is a crucial factor for ASIC technology mapping, and supergate technology proves to be an effective method for achieving this in EDA tools flow. However, we have observed that increasing the number of generated supergates can reduce delay, but this comes at the cost of an exponential increase in computation time. In this paper, we propose a parallel supergate computing method that addresses the tradeoff between time-consuming and delay optimization. The proposed method utilizes the input-constrained supergate pattern to parallelly generate the supergate candidates, and then filter the valid supergates as the results. Experiment results show the efficiency of the proposed method, for example, it can attain the improvement of 4x speedup in computation time and 10.1 in delay reduction with 32 threads.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
