低功耗并行刷新低温电荷锁定阵列
Parallel refreshed cryogenic charge-locking array with low power dissipation
AI总结：
本文针对毫开尔文温区大规模量子电路控制信号的功耗限制问题，提出了一种功率高效的电荷锁定阵列实现方法，以满足严格热预算下的低温集成需求。
摘要：
构建包含数百万个低温量子比特的大规模量子电路，需要一种高效的方式来提供大量经典控制信号。鉴于从室温允许的直接连接数量有限，多级信号复用变得至关重要。实现这一任务的硬件堆叠高度依赖于控制电子器件最底层的实现方式，其中一个悬而未决的问题是毫开尔文（mK）温区集成的可行性。只要不受所涉及的大功耗限制，这种集成在信号传输和导线互连方面是首选方案。必须开发优先考虑功率效率的新型低温电子器件，以满足严格的热预算要求。在本文中，我们提出了一种功率高效的方法来实现电荷锁定阵列。
英文摘要：
To build a large scale quantum circuit comprising millions of cryogenic qubits will require an efficient way to supply large numbers of classic control signals. Given the limited number of direct connections allowed from room temperature, multiple level of signal multiplexing becomes essential. The stacking of hardware to accomplish this task is highly dependent on the lowest level implementation of control electronics, of which an open question is the feasibility of mK integration. Such integration is preferred for signal transmission and wire interconnection, provided it is not limited by the large power dissipation involved. Novel cryogenic electronics that prioritises power efficiency has to be developed to meet the tight thermal budget. In this paper, we present a power efficient approach to implement charge-locking array.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
