释放SFQ算术电路中T1单元的潜能
Unleashing the Power of T1-cells in SFQ Arithmetic Circuits
AI总结：
针对RSFQ超导电路面积开销大的问题，提出支持T1-FF的两阶段SFQ技术映射方法，通过替换单元与多相重定时，实现面积平均缩减6%、128位加法器最高缩减25%的效果。
摘要：
快速单磁通量子（RSFQ）是一种主流的低温超导电子（SCE）技术，具备极低功耗与高速特性。然而，实现超大规模集成电路（VLSI）复杂度的RSFQ系统面临诸多挑战，例如门级流水线与路径平衡带来的巨大面积开销，而RSFQ有限的布图密度进一步加剧了这一问题。T1触发器（T1-FF）是一种充当脉冲计数器的RSFQ逻辑单元，使用T1-FF实现全加器功能仅需传统实现方案40%的面积，但该单元对输入信号时序施加了复杂约束，使其应用变得复杂。近期已有研究提出多相时钟技术以减轻门级流水线开销，利用多相时钟可高效控制扇入信号。我们提出了一种支持T1-FF的新型两阶段SFQ技术映射方法：首先将SFQ网络中的兼容部分替换为高效的T1-FF，随后应用多相重定时为每个逻辑门分配时钟相位并插入D触发器（DFF）以满足输入时序要求。采用我们的设计流程，SFQ网络的面积平均减少6%，在优化128位加法器时面积降幅最高可达25%。
英文摘要：
Rapid single-flux quantum (RSFQ), a leading cryogenic superconductive electronics (SCE) technology, offers extremely low power dissipation and high speed. However, implementing RSFQ systems at VLSI complexity faces challenges, such as substantial area overhead from gate-level pipelining and path balancing, exacerbated by RSFQ's limited layout density. T1 flip-flop (T1-FF) is an RSFQ logic cell operating as a pulse counter. Using T1-FF the full adder function can be realized with only 40% of the area required by the conventional realization. This cell however imposes complex constraints on input signal timing, complicating its use. Multiphase clocking has been recently proposed to alleviate gate-level pipelining overhead. The fanin signals can be efficiently controlled using multiphase clocking. We present the novel two-stage SFQ technology mapping methodology supporting the T1-FF. Compatible parts of the SFQ network are first replaced by the efficient T1-FFs. Multiphase retiming is next applied to assign clock phases to each logic gate and insert DFFs to satisfy the input timing. Using our flow, the area of the SFQ networks is reduced, on average, by 6% with up to 25% reduction in optimizing the 128-bit adder.
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