采用非整数倍逻辑的3 V可编程约瑟夫森结阵列的验证
Demonstration of 3 V Programmable Josephson Junction Arrays Using Non-Integer-Multiple Logic
AI总结：
本研究提出一种用于可编程约瑟夫森电压标准的非整数倍逻辑，可容忍超导短路导致的结缺失，证明了序列完备性并给出整数表示算法，最终实现3 V可编程约瑟夫森结阵列的设计制备与参数测试。
摘要：
本文展示了一种可用于可编程约瑟夫森电压标准的新型整数表示可编程逻辑。与常规二进制逻辑或三进制逻辑不同，该逻辑可使大多数比特位的结数为可变整数值，因此能够容忍因超导短路导致的结缺失，且分段效率与三进制逻辑接近。本文通过数学递归方法证明了该逻辑序列的完备性，随后基于证明过程提出了一种新的整数表示算法，并分析了每个比特位的容错结数：前两个比特位无法容忍结缺失，其余比特位可容忍1个到数百个结缺失。由于序列各比特位之间的倍数不固定，该逻辑被命名为非整数倍逻辑。最后，本文介绍了采用该逻辑的3 V可编程约瑟夫森结阵列的设计与制备过程，并给出了特征参数的测量与分析结果。
英文摘要：
This article demonstrates a new kind of programmable logic for the representation of an integer that can be used for the programmable Josephson voltage standard. It can enable the numbers of junctions in most bits to be variable integer values, which is different from normal binary logic or ternary logic. Consequently, missing junctions due to superconducting short circuits can be tolerated under this logic. This logic can also have nearly the same segmentation efficiency as ternary logic. The completeness of the sequences using this logic is proven by the recursive method in mathematics in this paper. After that, a new algorithm for the representation of integers is presented according to the proven process, and an analysis of the number of fault-tolerant junctions for each bit is provided. Although the first and second bits are not tolerant to missing junctions, bits beyond these can tolerate one to hundreds of missing junctions. Due to the non-fixed multiples between the bits of the sequence, this logic is called non-integer-multiple logic. Finally, the design and fabrication of a 3 V programmable Josephson junction array using this logic are described, and the measurements and analysis of the characteristic parameters are presented.
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