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arXiv 2402.09780cs.LG
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TinyCL:一种用于自主系统持续学习的高效硬件架构

TinyCL: An Efficient Hardware Architecture for Continual Learning on Autonomous Systems

Department of Electronics and Telecommunications, Politecnico di Torino(电子工程与电信系,都灵理工学院);eBrain Lab, Division of Engineering, New York University Abu Dhabi(eBrain实验室,工程系,纽约大学阿布扎克分校)

Eugenio Ressa, Alberto Marchisio, Maurizio Martina, Guido Masera, Muhammad Shafique

AI总结:

本文提出TinyCL硬件架构,首次在资源受限自主系统上实现持续学习,通过蛇形滑动窗口和可重构乘加单元加速前向与反向传播,在CIFAR10上较GPU实现58倍加速。

摘要:

持续学习(CL)范式包括持续更新深度神经网络(DNN)模型的参数,以逐步学习执行新任务,同时不降低在先前任务上的性能,即避免所谓的灾难性遗忘。然而,基于CL的自主系统中的DNN参数更新极其消耗资源。现有的DNN加速器不能直接用于CL,因为它们仅支持前向传播的执行。只有少数先前架构执行反向传播和权重更新,但它们缺乏对CL的控制和管理。为此,我们设计了一种硬件架构TinyCL,用于在资源受限的自主系统上执行CL。它由一个执行前向和反向传播的处理单元,以及一个管理基于内存的CL工作负载的控制单元组成。为了最小化内存访问,卷积层的滑动窗口以蛇形方式移动。此外,乘加单元可以在运行时重新配置以执行不同的操作。据我们所知,我们提出的TinyCL是第一个在自主系统上执行CL的硬件加速器。我们采用65 nm CMOS技术节点和传统ASIC设计流程综合了完整的TinyCL架构。它在CIFAR10数据集上的Conv + ReLU + Dense模型上执行1个训练周期需要1.76秒,而使用Nvidia Tesla P100 GPU对同一模型进行1个训练周期需要103秒,从而实现了58倍的加速,在4.74 mm²的芯片面积上功耗为86 mW。

英文摘要:

The Continuous Learning (CL) paradigm consists of continuously evolving the parameters of the Deep Neural Network (DNN) model to progressively learn to perform new tasks without reducing the performance on previous tasks, i.e., avoiding the so-called catastrophic forgetting. However, the DNN parameter update in CL-based autonomous systems is extremely resource-hungry. The existing DNN accelerators cannot be directly employed in CL because they only support the execution of the forward propagation. Only a few prior architectures execute the backpropagation and weight update, but they lack the control and management for CL. Towards this, we design a hardware architecture, TinyCL, to perform CL on resource-constrained autonomous systems. It consists of a processing unit that executes both forward and backward propagation, and a control unit that manages memory-based CL workload. To minimize the memory accesses, the sliding window of the convolutional layer moves in a snake-like fashion. Moreover, the Multiply-and-Accumulate units can be reconfigured at runtime to execute different operations. As per our knowledge, our proposed TinyCL represents the first hardware accelerator that executes CL on autonomous systems. We synthesize the complete TinyCL architecture in a 65 nm CMOS technology node with the conventional ASIC design flow. It executes 1 epoch of training on a Conv + ReLU + Dense model on the CIFAR10 dataset in 1.76 s, while 1 training epoch of the same model using an Nvidia Tesla P100 GPU takes 103 s, thus achieving a 58x speedup, consuming 86 mW in a 4.74 mm2 die.

机构、总结、中文摘要均由AI分析而来,可能存在错误,请以论文正文为准。

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