一种用于存内计算的3D忆阻器架构：以SHA3为例的演示
A 3D Memristor Architecture for In-Memory Computing Demonstrated with SHA3
AI总结：
本文提出一种基于混合CMOS-忆阻器技术的3D忆阻器架构，通过垂直交叉阵列实现SHA3逻辑与循环位移，解决了传统计算机内存瓶颈，并在尺寸和能耗上优于现有设计。
摘要：
安全是一个日益严重的问题，需要硬件支持。忆阻器为实现硬件支持的安全提供了一种替代技术。本文提出了一种特定技术，利用混合CMOS-忆阻器技术的优势，以SHA3为例进行演示，相较于仅使用忆阻器技术的实现具有优越性。在所提出的技术中，SHA3在一组垂直交叉阵列中实现，这些阵列的结构旨在促进逻辑实现和循环位移（Rho操作），这可能是忆阻器阵列中执行的最复杂操作。Rho操作本身由CMOS多路复用器（MUXs）实现。所提出的加速器无待机功耗，并规避了传统计算机中的内存访问瓶颈。此外，我们的设计隐藏了来自I/O接口的中间值，并在尺寸和能耗方面优于最先进的基于忆阻器的设计。演示SHA3的忆阻器实现为在信息安全应用中利用忆阻器提供了动力。
英文摘要：
Security is a growing problem that needs hardware support. Memristors provide an alternative technology for hardware-supported security implementation. This paper presents a specific technique that utilizes the benefits of hybrid CMOS-memristors technology demonstrated with SHA3 over implementations that use only memristor technology. In the proposed technique, SHA3 is implemented in a set of perpendicular crossbar arrays structured to facilitate logic implementation and circular bit rotation (Rho operation), which is perhaps the most complex operation in SHA3 when carried out in memristor arrays. The Rho operation itself is implemented with CMOS multiplexers (MUXs). The proposed accelerator is standby power-free and circumvents the memory access bottleneck in conventional computers. In addition, our design obscures the intermediate values from the I/O interface and outperforms the state-of-the-art memristor-based designs in terms of size and energy. Demonstrating the memristor implementation of SHA3 provides an impetus for utilizing memristors in information security applications.
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