基于Haar-like级联分类器的人脸检测在低成本ARM big.LITTLE非对称架构上的加速与能耗优化
Acceleration and energy consumption optimization in cascading classifiers for face detection on low-cost ARM big.LITTLE asymmetric architectures
AI总结：
本文针对低成本ARM big.LITTLE非对称多核处理器，提出基于OmpSs任务模型与动态调度策略的级联分类器人脸检测加速与能耗优化机制，并验证其能效优于同构架构。
摘要：
本文提出了一种机制，用于加速并优化基于Haar-like级联分类器的人脸检测软件的能量消耗，利用低成本非对称多核处理器（AMPs）在有限功耗预算下的特性。文中提出了一种建模与任务调度/分配方法，以高效利用big.LITTLE ARM处理器上的现有特性，包括：（I）针对并行计算的源代码改编，通过应用OmpSs编程模型实现代码加速，这是一种基于任务的编程模型，能够以透明方式处理任务间的数据依赖性；（II）不同的OmpSs任务分配策略，这些策略考虑了处理器的不对称性，并能根据其特定特性以更高效的方式动态设置处理资源。所提出的机制可有效应用于利用低成本、低能耗多核嵌入式设备上现有的处理元件，执行基于级联分类器的目标检测算法。尽管这些分类器在计算机视觉领域为检测算法提供了最佳结果，但其高计算需求阻碍了它们在实时要求下在这些设备上的使用。最后，我们将基于非对称多核处理器并配合合适任务调度的异构架构的能效，与同构对称架构的能效进行了比较。
英文摘要：
This paper proposes a mechanism to accelerate and optimize the energy consumption of a face detection software based on Haar-like cascading classifiers, taking advantage of the features of low-cost Asymmetric Multicore Processors (AMPs) with limited power budget. A modelling and task scheduling/allocation is proposed in order to efficiently make use of the existing features on big.LITTLE ARM processors, including: (I) source-code adaptation for parallel computing, which enables code acceleration by applying the OmpSs programming model, a task-based programming model that handles data-dependencies between tasks in a transparent fashion; (II) different OmpSs task allocation policies which take into account the processor asymmetry and can dynamically set processing resources in a more efficient way based on their particular features. The proposed mechanism can be efficiently applied to take advantage of the processing elements existing on low-cost and low-energy multi-core embedded devices executing object detection algorithms based on cascading classifiers. Although these classifiers yield the best results for detection algorithms in the field of computer vision, their high computational requirements prevent them from being used on these devices under real-time requirements. Finally, we compare the energy efficiency of a heterogeneous architecture based on asymmetric multicore processors with a suitable task scheduling, with that of a homogeneous symmetric architecture.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
