用于高k电介质沉积的高压溅射：值得尝试吗？
High Pressure Sputtering For Kigh-k Dielectric Deposition. Is It Worth Trying?
AI总结：
本研究采用高压溅射法制备高k电介质，验证了富钪酸钆的高介电常数特性及钛栅清除效应对硅、磷化铟衬底界面层的减薄作用，证明该方法具有应用潜力。
摘要：
我们的研究团队采用一种非标准方法——高压溅射，研究高介电常数电介质的沉积。本次研究的电介质包括从电介质靶材沉积的钪酸钆，以及从金属靶材沉积、经原位等离子体氧化处理的氧化钆。化学计量比的钪酸钆在退火后介电常数略有提升，但富钪酸钆（通过纳米叠层退火生长）的有效介电常数高达21，且与硅的界面处无明显SiO₂层。另一方面，用金属钆靶制备的叠层结构的SiO₂界面层厚度小于0.7 nm，可通过钛栅极的清除作用进一步减薄。事实上，这种清除效应还首次在磷化铟衬底上得到验证，获得了仅2.1 nm的低电容等效厚度。
英文摘要：
Our research group studies the deposition of high permittivity dielectrics by a non-standard method: high-pressure sputtering. The dielectrics studied here are gadolinium scandate deposited from dielectric targets, and gadolinium oxide deposited from a metallic target, with an in situ plasma oxidation. The stoichiometric gadolinium scandate presents a slight permittivity boost after annealing, but with gadolinium-rich scandate (grown with an annealing of a nanolaminate) the dielectric shows a high effective permittivity of 21 and no noticeable SiO2 layer at the interface with Si. On the other hand, the stacks fabricated with the metallic Gd target have a SiO2 interface less than 0.7 nm thick that can be further reduced by scavenging with Ti gates. In fact, this scavenging effect is also demonstrated for the first time with indium phosphide substrates, obtaining a low capacitance equivalent thickness of only 2.1 nm.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
