CIM-MLC：面向存内计算加速器的多级编译栈
CIM-MLC: A Multi-level Compilation Stack for Computing-In-Memory Accelerators
AI总结：
本文提出 CIM-MLC 多级编译框架，通过通用硬件抽象支持多样化 CIM 加速器，并跨架构层次联合优化映射、调度与指令生成。
摘要：
近年来，各类存内计算（CIM）处理器相继被提出，并展现出优于传统架构的性能。为充分释放各种 CIM 架构的潜力，例如器件精度、crossbar 尺寸和 crossbar 数量，有必要开发能够充分感知 CIM 架构细节与实现多样性的编译工具。然而，由于当前流行的开源编译栈缺乏架构支持，现有 CIM 设计要么手动部署网络，要么构建自己的编译器，这既耗时又耗费人力。尽管一些工作将特定 CIM 器件编程接口暴露给编译器，但它们通常绑定于固定的 CIM 架构，缺乏支持具有不同计算粒度的 CIM 架构的灵活性。另一方面，现有编译工作通常只考虑有限操作类型的调度，例如受 crossbar 约束的矩阵-向量乘法。与传统处理器不同，CIM 加速器的特点在于其多样化的架构、电路和器件；如果我们寻求充分挖掘 CIM 带来的优势，就不能简单地通过单一层次对其进行抽象。因此，我们提出 CIM-MLC，这是一种面向通用 CIM 架构的通用多级编译框架。我们首先为 CIM 架构和计算模式建立通用硬件抽象，以表示各种 CIM 加速器。基于所提出的抽象，CIM-MLC 能够将任务编译到广泛的、具有不同器件、架构和编程接口的 CIM 加速器上。更重要的是，与现有编译工作相比，CIM-MLC 能够跨多个架构层次探索映射和调度策略，这些策略构成了一个既易处理又有效的设计空间，从而获得更好的调度和指令生成结果。
英文摘要：
In recent years, various computing-in-memory (CIM) processors have been presented, showing superior performance over traditional architectures. To unleash the potential of various CIM architectures, such as device precision, crossbar size, and crossbar number, it is necessary to develop compilation tools that are fully aware of the CIM architectural details and implementation diversity. However, due to the lack of architectural support in current popular open-source compiling stacks, existing CIM designs either manually deploy networks or build their own compilers, which is time-consuming and labor-intensive. Although some works expose the specific CIM device programming interfaces to compilers, they are often bound to a fixed CIM architecture, lacking the flexibility to support the CIM architectures with different computing granularity. On the other hand, existing compilation works usually consider the scheduling of limited operation types (such as crossbar-bound matrix-vector multiplication). Unlike conventional processors, CIM accelerators are featured by their diverse architecture, circuit, and device, which cannot be simply abstracted by a single level if we seek to fully explore the advantages brought by CIM. Therefore, we propose CIM-MLC, a universal multi-level compilation framework for general CIM architectures. We first establish a general hardware abstraction for CIM architectures and computing modes to represent various CIM accelerators. Based on the proposed abstraction, CIM-MLC can compile tasks onto a wide range of CIM accelerators having different devices, architectures, and programming interfaces. More importantly, compared with existing compilation work, CIM-MLC can explore the mapping and scheduling strategies across multiple architectural tiers, which form a tractable yet effective design space, to achieve better scheduling and instruction generation results.
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