IPU：灵活的硬件自省单元
IPU: Flexible Hardware Introspection Units
AI总结：
本文提出IPU硬件自省单元，以实时低开销监控芯片现场行为，解决硬件A/B测试、混淆硬件与软件问题，面积开销<1%且功耗<25mW，实现预取器评估、周期堆栈等新分析。
摘要：
现代芯片设计日益复杂，使得开发者在真实工作负载运行时难以获取有关硬件行为的有意义见解。硬件自省旨在通过使硬件自身能够观察并报告其内部操作来解决这一问题——尤其是在现场，即芯片执行真实世界软件和工作负载的环境中。当前，硬件自省可以解决的三个关键问题迫在眉睫：现场硬件的A/B测试、混淆硬件以及混淆软件——后者阻碍芯片设计者获取其芯片在现场行为中的见解。为此，目标是实现在现场以实时速度、无减速、最小功耗开销的情况下监控芯片硬件行为，从而获得关于芯片行为和工作负载的见解。本文实现了系统架构，并介绍了自省处理单元（IPU）——作为实现上述目标的一种解决方案。我们通过案例研究展示了硬件自省在三个问题上的应用，并实现了RTL级原型。在这些案例研究中，我们表明，一个在7nm工艺下面积开销小于1%、总功耗小于25毫瓦的IPU能够产生以前难以想象的分析：在部署前评估现场指令预取器，为任意程序创建每指令周期堆栈，以及详细描述硬件模块的细粒度逐周期利用率。
英文摘要：
Modern chip designs are increasingly complex, making it difficult for developers to glean meaningful insights about hardware behavior while real workloads are running. Hardware introspection aims to solve this by enabling the hardware itself to observe and report on its internal operation - especially in the field, where the chip is executing real-world software and workloads. Three key problems are now imminent that hardware introspection can solve: A/B testing of hardware in the field, obfuscated hardware, and obfuscated software which prevents chip designers from gleaning insights on in the field behavior of their chips. To this end, the goal is to enable monitoring chip hardware behavior in the field, at real-time speeds with no slowdowns, with minimal power overheads, and thereby obtain insights on chip behavior and workloads. This paper implements the system architecture for and introduces the Introspection Processing Unit (IPU) - one solution to said goal. We perform case studies exemplifying the application of hardware introspection to the three problems through an IPU and implement an RTL level prototype. Across the case studies, we show that an IPU with area overhead less than 1 percent at 7nm, and overall power consumption of less than 25 mW is able to create previously inconceivable analysis: evaluating instruction prefetchers in the field before deployment, creating per-instruction cycles stacks of arbitrary programs, and detailing fine-grained cycle-by-cycle utilization of hardware modules.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
