基于排序网络快速进位生成逻辑的高速(7,2)压缩器
High-Speed (7,2) Compressor Using A Fast Carry-Generation Logic based on Sorting Network
AI总结：
本文提出一种基于排序网络快速进位生成逻辑的高速(7,2)压缩器，仅需11个逻辑阶段，在7行8列二进制阵列测试中性能优于以往设计，适用于乘法及密码学硬件。
摘要：
快速二进制压缩器是许多基础数字计算单元的主要组件。本文提出了一种带有快速进位生成逻辑的高速(7,2)压缩器。该进位生成逻辑基于排序网络，可在2个逻辑阶段内生成进位，而非先前教科书式全加器中的3个阶段。配合调整后的全加器逻辑，所提出的(7,2)压缩器仅需使用11个基本逻辑阶段。在具有7行8列的二进制阵列中测试此新设计，结果表明该设计比以前的设计具有更高的性能。该方法适用于乘法设计或其他密码学硬件块中的高性能场景。
英文摘要：
Fast binary compressors are the main components of many basic digital calculation units. In this paper, a high-speed (7,2) compressor with a fast carry-generation logic is proposed. The carry-generation logic is based on the sorting network, and it can generate a carry bit within 2 logical stages other than 3 stages as in previous school book full adders. Collaborating with the adjusted full adder logic, the proposed (7,2) compressor achieves using only 11 basic logical stages. Testing this new design in a binary arry with 7 rows and 8 columns, and the result shows that this design have higher proformance than previous designs. This method is suitable for high proformance cases in multiplication design or other cryptography hardware blocks.
机构、总结、中文摘要均由AI分析而来，可能存在错误，请以论文正文为准。
