parti-gem5：gem5 时序模式的并行化
parti-gem5: gem5's Timing Mode Parallelised
AI总结：
本文提出 parti-gem5，通过并行化 gem5 时序仿真内核提升吞吐量，并支持 O3CPU 与 Ruby 模型，在 120 核 ARM MPSoC 上最高获得 42.7 倍加速且多数误差低于 15%。
摘要：
详细时序模型是多处理器片上系统（MPSoC）设计空间探索中不可或缺的工具。随着核心数量持续增加，存储层次结构和互连拓扑的复杂性也在不断增长，这使得对设计决策进行准确预测比以往任何时候都更具挑战性。在此背景下，开源全系统模拟器（FSS）gem5 凭借其灵活性以及丰富而可靠的详细时序模型集合，成为 MPSoC 设计空间探索的常用选择。然而，其单线程仿真内核严重限制了吞吐量。为应对这一挑战，我们提出 parti-gem5，这是 gem5 的一个扩展，可在现代多核仿真主机上实现并行时序仿真。与以往工作不同，parti-gem5 支持 gem5 的时序模式、O3CPU，以及 Ruby 的自定义缓存和互连模型。与参考的单线程仿真相比，在一台 64 核 x86-64 主机系统上仿真 120 核 ARM MPSoC 时，我们实现了最高 42.7 倍的加速。尽管我们的方法会引入时序偏差，但在大多数情况下，总仿真时间的误差低于 15%。
英文摘要：
Detailed timing models are indispensable tools for the design space exploration of Multiprocessor Systems on Chip (MPSoCs). As core counts continue to increase, the complexity in memory hierarchies and interconnect topologies is also growing, making accurate predictions of design decisions more challenging than ever. In this context, the open-source Full System Simulator (FSS) gem5 is a popular choice for MPSoC design space exploration, thanks to its flexibility and robust set of detailed timing models. However, its single-threaded simulation kernel severely hampers its throughput. To address this challenge, we introduce parti-gem5, an extension of gem5 that enables parallel timing simulations on modern multi-core simulation hosts. Unlike previous works, parti-gem5 supports gem5's timing mode, the O3CPU, and Ruby's custom cache and interconnect models. Compared to reference single-thread simulations, we achieved speedups of up to 42.7x when simulating a 120-core ARM MPSoC on a 64-core x86-64 host system. While our method introduces timing deviations, the error in total simulated time is below 15% in most cases.
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