一种用于容错量子纠错的低温忆阻神经解码器
A Cryogenic Memristive Neural Decoder for Fault-tolerant Quantum Error Correction
AI总结：
本研究针对容错量子纠错需求，设计基于忆阻交叉阵列存内计算架构的低温神经解码器，通过硬件感知再训练缓解器件非理想性影响，恢复表面码伪阈值，为集成容错QEC硬件提供路径。
摘要：
用于量子纠错（QEC）的神经解码器依靠神经网络对从纠错码中提取的校验子进行分类，并找到合适的恢复算子，以保护逻辑信息免受错误影响。神经解码器能够适应硬件噪声和长期漂移，这使其成为容错量子架构中极具潜力的候选组件。然而，鉴于其可扩展性有限，在拥有数百万量子比特的容错量子计算机中，将小规模（局部）神经解码器作为多级解码方案的第一阶段是审慎的做法。在这种情况下，最大限度缩短解码时间以匹配稳定测量频率，并实现与量子处理单元（QPU）的紧密共集成，是人们高度期望的目标。神经解码器的低温实现不仅能提升更高级解码器的性能，还能最大限度减少通信延迟，缓解布线瓶颈。在本研究中，我们设计并分析了一种基于存内计算（IMC）架构的神经解码器，该架构采用阻变存储器件的交叉阵列，既用于存储神经解码器的突触权重，又用于执行模拟矩阵-向量乘法。在实验测量支撑的仿真中，我们研究了基于氧化钛（TiOx）的忆阻器件的非理想特性对解码保真度的影响。我们开发了硬件感知的再训练方法来缓解保真度损失，恢复了距离为3的表面码下理想解码器的伪阈值。本研究为面向集成容错量子纠错的可扩展、快速、低功耗低温存内计算硬件提供了一条可行路径。
英文摘要：
Neural decoders for quantum error correction (QEC) rely on neural networks to classify syndromes extracted from error correction codes and find appropriate recovery operators to protect logical information against errors. Its ability to adapt to hardware noise and long-term drifts make neural decoders a promising candidate for inclusion in a fault-tolerant quantum architecture. However, given their limited scalability, it is prudent that small-scale (local) neural decoders are treated as first stages of multi-stage decoding schemes for fault-tolerant quantum computers with millions of qubits. In this case, minimizing the decoding time to match the stabilization measurements frequency and a tight co-integration with the QPUs is highly desired. Cryogenic realizations of neural decoders can not only improve the performance of higher stage decoders, but they can minimize communication delays, and alleviate wiring bottlenecks. In this work, we design and analyze a neural decoder based on an in-memory computation (IMC) architecture, where crossbar arrays of resistive memory devices are employed to both store the synaptic weights of the neural decoder and perform analog matrix-vector multiplications. In simulations supported by experimental measurements, we investigate the impact of TiOx-based memristive devices' non-idealities on decoding fidelity. We develop hardware-aware re-training methods to mitigate the fidelity loss, restoring the ideal decoder's pseudo-threshold for the distance-3 surface code. This work provides a pathway to scalable, fast, and low-power cryogenic IMC hardware for integrated fault-tolerant QEC.
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