通过 BCH 码的优化设计增强多级 NOR 和 NAND 闪存中的数据存储可靠性与纠错能力
Enhancing Data Storage Reliability and Error Correction in Multilevel NOR and NAND Flash Memories through Optimal Design of BCH Codes
AI总结：
针对多级 NOR/NAND 闪存的可靠性问题，本文通过并行、流水线及 XOR 共享优化 BCH 解码器，并经 VHDL 与 Xilinx ISE 验证可降低纠错时间和硬件开销。
摘要：
最新一代闪存中晶体管尺寸的缩小导致这些设计出现编程和数据擦除问题。因此，确保可靠的数据存储已成为这些存储器结构面临的一项重大挑战。为应对这一挑战，BCH（Bose-Chaudhuri-Hocquenghem）码等纠错码被用于这些存储器的控制器中。在对 BCH 码进行解码时，两个关键因素是纠错延迟以及每个子模块的硬件需求。本文提出了一种有效解决方案，以提高纠错速度并优化解码器电路的效率。该方案建议为 BCH 解码器的各子模块实现并行架构，并采用流水线技术。此外，为降低 BCH 解码器模块的硬件需求，本文引入了一种基于 XOR 共享的算法，以消除 Chien 搜索模块中的冗余门。所提出的解码器使用 VHDL 硬件描述语言进行仿真，随后使用 Xilinx ISE 软件进行综合。仿真结果表明，与同类方法相比，所提出的算法不仅显著缩短了纠错时间，还明显降低了 BCH 解码器模块的硬件开销。
英文摘要：
The size reduction of transistors in the latest flash memory generation has resulted in programming and data erasure issues within these designs. Consequently, ensuring reliable data storage has become a significant challenge for these memory structures. To tackle this challenge, error-correcting codes like BCH (Bose-Chaudhuri-Hocquenghem) codes are employed in the controllers of these memories. When decoding BCH codes, two crucial factors are the delay in error correction and the hardware requirements of each sub-block. This article proposes an effective solution to enhance error correction speed and optimize the decoder circuit's efficiency. It suggests implementing a parallel architecture for the BCH decoder's sub-blocks and utilizing pipeline techniques. Moreover, to reduce the hardware requirements of the BCH decoder block, an algorithm based on XOR sharing is introduced to eliminate redundant gates in the search Chien block. The proposed decoder is simulated using the VHDL hardware description language and subsequently synthesized with Xilinx ISE software. Simulation results indicate that the proposed algorithm not only significantly reduces error correction time but also achieves a noticeable reduction in the hardware overhead of the BCH decoder block compared to similar methods.
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