Corona:新兴纳米光子技术的系统影响
Corona: System Implications of Emerging Nanophotonic Technology
AI总结:
本文提出3D纳米光子众核架构Corona,利用光通信实现10 TFLOPS性能、10 TB/s内存带宽和20 TB/s核间带宽,并在模拟中相较电连接方案显著提升内存密集型负载性能且降低功耗。
摘要:
我们预计,在未来十年中,众核微处理器将把每芯片性能从10 gigaflop提升到10 teraflop范围。为支持这种性能提升,内存带宽和核间带宽也必须按数量级扩展。引脚限制、电信号传输的能量成本,以及芯片长度全局互连线的不可扩展性,都是显著的带宽障碍。硅纳米光子技术的最新进展有望在可接受的功耗水平下满足这些栈外和栈内带宽需求。Corona是一种3D众核架构,采用纳米光子通信实现核间通信以及到内存或I/O设备的栈外通信。其峰值浮点性能为10 teraflops。密集波分复用的光连接内存模块提供每秒10 terabyte的内存带宽。一个光子交叉开关以每秒20 terabyte的带宽完全互连其256个低功耗多线程核心。我们模拟了一个运行合成基准测试和按比例扩展版本SPLASH-2基准套件的1024线程Corona系统。我们认为,与采用相同栈内互连功耗的电连接众核替代方案相比,Corona可在许多内存密集型工作负载上提供2至6倍的性能,同时降低功耗。
英文摘要:
We expect that many-core microprocessors will push performance per chip from the 10 gigaflop to the 10 teraflop range in the coming decade. To support this increased performance, memory and inter-core bandwidths will also have to scale by orders of magnitude. Pin limitations, the energy cost of electrical signaling, and the non-scalability of chip-length global wires are significant bandwidth impediments. Recent developments in silicon nanophotonic technology have the potential to meet these off- and on- stack bandwidth requirements at acceptable power levels. Corona is a 3D many-core architecture that uses nanophotonic communication for both inter-core communication and off-stack communication to memory or I/O devices. Its peak floating-point performance is 10 teraflops. Dense wavelength division multiplexed optically connected memory modules provide 10 terabyte per second memory bandwidth. A photonic crossbar fully interconnects its 256 low-power multithreaded cores at 20 terabyte per second bandwidth. We have simulated a 1024 thread Corona system running synthetic benchmarks and scaled versions of the SPLASH-2 benchmark suite. We believe that in comparison with an electrically-connected many-core alternative that uses the same on-stack interconnect power, Corona can provide 2 to 6 times more performance on many memory-intensive workloads, while simultaneously reducing power.
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